Inventor

CHEN SHENG-HSIUNG

TW128 patents

⚠️ This page may combine multiple inventors who share the name “CHEN SHENG-HSIUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN SHENG-HSIUNG

TAIWAN SEMICONDUCTOR MFG CO LTD

System and method for back side signal routing

Integrated circuit and method of forming same and a system

Method of designing semiconductor device

Method for generating layout diagram including cell having pin patterns and semiconductor device based on same

Integrated circuit and method of forming same and a system

Method for generating layout diagram including protruding pin cell regions and semiconductor device based on same

Logic cell structure and integrated circuit with the logic cell structure

Method and system of expanding set of standard cells which comprise a library

Layout for semiconductor device including via pillar structure

Integrated circuit, system for and method of forming an integrated circuit

Method of modifying cell and global connection routing method

Integrated circuit having a high cell density

Integrated circuit and method of forming same and a system

Integrated circuit fin structure manufacturing method

System for designing semiconductor device

Integrated circuit and method of forming same and a system

Circuit layouts and related methods

Integrated circuit and layout method for standard cell structures

Pin modification for standard cells

Method for manufacturing a cell having pins and semiconductor device based on same

Integrated circuit fin layout method, system, and structure

Pin modification for standard cells

Semiconductor device with cell region, method of generating layout diagram and system for same

Integrated circuit device with improved layout

Method of designing semiconductor device and system for implementing the method

Method of fabricating integrated circuit having staggered conductive features

Integrated circuit structure

TAIWAN SEMICONDUCTOR MFG

Method of improved copper gap fill

Method of improving copper pad adhesion

Selective growth of copper for advanced metallization

Fabrication process for metal-insulator-metal capacitor with low gate resistance

Modified pad for copper/low-k

Method of improving copper pad adhesion

Method of wafer edge damage inspection

Method of forming dual damascene structure

Microelectronic capacitor structure compatible with copper containing microelectronic conductor layer processing

Fabrication process for metal-insulator-metal capacitor with low gate resistance

Integration process for Al pad

Method for preventing seed layer oxidation for high aspect gap fill

Method for marking a wafer without inducing flat edge particle problem

Selective formation of metal gate for dual gate oxide application

Liquid phase deposition of a silicon oxide layer for use as a liner on the surface of a dual damascene opening in a low dielectric constant layer

Reduction of electromigration in dual damascene connector

Method of improving pad metal adhesion

Epitaxial plasma enhanced chemical vapor deposition (PECVD) method providing epitaxial layer with attenuated defects

Method for fabricating metal gates in deep sub-micron devices

NAT SCIENCE COUNCIL

Method of forming a boron-doped diamond film by chemical vapor deposition

Process for depositing diamond by chemical vapor deposition

SYNOPSYS TAIWAN CO LTD

Multiple level spine routing

CHANG FONG-YUAN

Multiple level spine routing