Inventor

GILL MANZUR

US76 patents

⚠️ This page may combine multiple inventors who share the name “GILL MANZUR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GILL MANZUR

TEXAS INSTRUMENTS INC

Segmented, multiple-decoder memory array and method for programming a memory array

Diffusionless conductor/oxide semiconductor field effect transistor and methods for making and using the same

Method of making contract-free floating-gate memory array with silicided buried bitlines and with single-step defined floating gates

Electrically programmable, electrically erasable memory array cell with field plate

Diffusionless source/drain conductor electrically-erasable, electrically-programmable read-only memory and method for making and using the same

Hot electron programmable, tunnel electron erasable contactless EEPROM

Process for minimizing lateral distance between elements in an integrated circuit by using sidewall spacers

Method of making EPROM with separate erasing and programming regions

Virtual ground memory cell array

EEPROM cell array with tight erase distribution

Cross-point contact-free array with a high-density floating-gate structure

Floating-gate memory array with silicided buried bitlines

Method for programming EEPROM memory arrays

Programming of an electrically-erasable, electrically-programmable, read-only memory array

Method of manufacturing an EEPROM with trench-isolated bitlines

Nonvolatile memory cell with field-plate switch

Floating-gate memory array with silicided buried bitlines and with single-step-defined floating gates

Cross-point contact-free floating-gate memory array with silicided buried bitlines

Cross-point contact-free array with a high-density floating-gate structure

EEPROM with trench-isolated bitlines

Bit and block erasing of an electrically erasable and programmable read-only memory array

Cross-point contact-free floating-gate memory array with silicided buried bitlines

Floating-gate memory array with silicided buried bitlines and with single-step-defined floating gates

Electrically-erasable, electrically-programmable read-only memory cell

Method of making hot electron programmable, tunnel electron erasable contactless EEPROM

Electrically programmable and erasable memory cells with field plate conductor defined drain regions

Method of making an EEPROM cell with separate erasing and programming regions

Wordline driver circuit for EEPROM memory cell

Method of making nonvolatile memory array having cells with two tunelling windows

Method of making a high-speed 2-transistor cell for programmable/EEPROM devices with separate read and write transistors

Driving circuitry for EEPROM memory cell

Electrically-erasable, electrically-programmable read-only memory cell, an array of such cells and methods for making and using the same

Memory cell array having continuous-strip field-oxide regions

Method of making EEPROM array with buried N+ windows and with separate erasing and programming regions

MOSFET cell array

Memory cell array with LOCOS free isolation

Self-aligned field-plate isolation between active elements

CMOS memory cell array

OVONYX INC

Single level metal memory cell using chalcogenide cladding

Technique and apparatus for performing write operations to a phase change material memory device

Method of forming a phase-change memory cell using silicon on insulator low electrode in charcogenide elements

Silicon on insulator phase change memory

Using an MOS select gate for a phase change memory

Isolating phase change memories with schottky diodes and guard rings

Single level metal memory cell using chalcogenide cladding

NAT SEMICONDUCTOR CORP

Memory array utilizing multi-state memory cells

Method for forming field oxide regions

Low-voltage EEPROM using charge-pumped word lines

EEPROM devices with smaller cell size

INTEL CORP

Method and apparatus to program a phase change memory