Inventor
SMITH STEPHEN LEE
US19 patents
⚠️ This page may combine multiple inventors who share the name “SMITH STEPHEN LEE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SYNOPSYS INC
16 patentsUS9727675B2Aug 8, 2017
Parameter extraction of DFT
SYNOPSYS INC14 citations92
US10831957B2Nov 10, 2020
Simulation scaling with DFT and non-DFT
SYNOPSYS INC3 citations83
US10049173B2Aug 14, 2018
Parameter extraction of DFT
SYNOPSYS INC4 citations83
US9881111B2Jan 30, 2018
Simulation scaling with DFT and non-DFT
SYNOPSYS INC5 citations83
US9836563B2Dec 5, 2017
Iterative simulation with DFT and non-DFT
SYNOPSYS INC5 citations83
US10102318B2Oct 16, 2018
Atomic scale grid for modeling semiconductor structures and fabrication processes
SYNOPSYS INC2 citations73
US9852242B2Dec 26, 2017
Atomic scale grid for modeling semiconductor structures and fabrication processes
SYNOPSYS INC3 citations73
US10776560B2Sep 15, 2020
Mapping intermediate material properties to target properties to screen materials
SYNOPSYS INC3 citations72
US10516725B2Dec 24, 2019
Characterizing target material properties based on properties of similar materials
SYNOPSYS INC4 citations72
US10489212B2Nov 26, 2019
Adaptive parallelization for multi-scale simulation
SYNOPSYS INC5 citations72
US10417373B2Sep 17, 2019
Estimation of effective channel length for FinFETs and nano-wires
SYNOPSYS INC2 citations72
US10402520B2Sep 3, 2019
First principles design automation tool
SYNOPSYS INC3 citations72
US11249813B2Feb 15, 2022
Adaptive parallelization for multi-scale simulation
SYNOPSYS INC0 citations62
US10606968B2Mar 31, 2020
Atomic scale grid for modeling semiconductor structures and fabrication processes
SYNOPSYS INC1 citations62
US10706209B2Jul 7, 2020
Estimation of effective channel length for FinFETs and nano-wires
SYNOPSYS INC0 citations51
US10685156B2Jun 16, 2020
Multi-scale simulation including first principles band structure extraction
SYNOPSYS INC0 citations51