Inventor

HUANG YUAN-CHANG

TW61 patents

⚠️ This page may combine multiple inventors who share the name “HUANG YUAN-CHANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUANG YUAN-CHANG

TAIWAN SEMICONDUCTOR MFG

Post gate etch cleaning process for self-aligned gate mosfets

0.3 Micron aperture width patterning process

Method for patterning a polysilicon gate in deep submicron technology

Self-aligned contact structures using high selectivity etching

Spin-on-glass etchback planarization process using an oxygen plasma to remove an etchback polymer residue

One step smooth cylinder surface formation process in stacked cylindrical DRAM products

Sacrificial etchback layer for improved spin-on-glass planarization

Method of fabricating seamless tungsten plug employing tungsten redeposition and etch back

Planarization and etch back process for semiconductor layers

Test site and a method of monitoring via etch depths for semiconductor devices

Optimized planarization process for SOG filled vias

Process for cleaning an electrostatic chuck of a plasma etching apparatus

Etching method for extending i-line photolithography to 0.25 micron linewidth

Use of a novel capped anneal procedure to improve salicide formation

Two step etch back process having a convex and concave etch profile for improved etch uniformity across a substrate

Removal process for tungsten etchback precipitates

Method for spin etching sidewall spacers by acid vapor

Self-aligned contact structures using high selectivity etching

Method of improving refresh time in DRAM products

Multilayer interlevel dielectrics using phosphorus-doped glass

Method to remove residue of metal etch

In situ hot bake treatment that prevents precipitate formation after a contact layer etch back step

Post contact layer etch back process which prevents precipitate formation

Temporary self-aligned stop layer is applied on silicon sidewall

Method for making improved capacitors on dynamic random access memory having increased capacitance, longer refresh times, and improved yields

Dimple-free tungsten plug

Dimple-free tungsten etching back process

Method of reducing particles during the manufacturing of fin or cylinder capacitors on a wafer

Advanced titanium silicide process for very narrow polysilicon lines

Dimple elimination in a tungsten etch back process by reverse image patterning

Anti-type dosage as LDD implant

IND TECH RES INST

Bonding structure with compliant bumps

Method for bonding inner leads to bond pads without bumps and structures formed

Method for interconnecting a flat panel display having a non-transparent substrate and devices formed

Bonding structure with buffer layer and method of forming the same

Method for forming self-cleaning coating comprising hydrophobically-modified particles

Conductive bumps with non-conductive juxtaposed sidewalls

Coating composition, film prepared from the coating composition, and method for preparing the coating composition

Inorganic passivation material, method for forming the same, and inorganic passivation protective film produced therefrom

Wafer level package structure of optical-electronic device and method for making the same

Bonding structure with buffer layer and method of forming the same

Bonding structure with buffer layer and method of forming the same

Method for forming coating material and the material formed thereby

Method for fabricating conductive bumps with non-conductive juxtaposed sidewalls

Organic-inorganic hybrid resin, coating material, and composite structure

SCINOPHARM TAIWAN LTD

Crystalline form of olaparib and a process for preparing the same

Polymorphism for irinotecan free base

TAIWAN SEMICONDUCTOR MANUFACTO

Test site and a method of monitoring via etch depths for semiconductor devices

TAIWAN SEMICONDUCTOR MANFACTUR

LOCOS field oxide and field oxide process using silicon nitride spacers

EVONIK OPERATIONS GMBH

Gelled electrolyte and preparation method thereof