Inventor

HOOVER RUSSELL D

US38 patents

⚠️ This page may combine multiple inventors who share the name “HOOVER RUSSELL D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOOVER RUSSELL D

IBM

Dynamic virtual software pipelining on a network on chip

Multiple spacial indexes for dynamic scene management in graphics rendering

System for aligning bytes of variable multi-bytes length operand based on alu byte length and a number of unprocessed byte data

Network on chip with an I/O accelerator

Monitoring software pipeline performance on a network on chip

System and method for empty notification from peer cache units to global storage control unit in a multiprocessor data processing system

Network on chip that maintains cache coherency with invalidate commands

Network on chip that maintains cache coherency with invalidate commands

Network on chip with a low latency, high bandwidth application messaging interconnect

E-fuses for storing security version data

System and method for transfer of data between processors using a locked set, head and tail pointers

Snoop filter directory mechanism in coherency shared memory system

Method and apparatus for maintaining n-way associative directories utilizing a content addressable memory

Allocating cache for use as a dedicated local storage

Network on chip with minimum guaranteed bandwidth for virtual communications channels

Graphics rendering on a network on chip

Network on chip with partitions

Direct access of cache lock set data without backing memory

Transferring architected state between cores

Method and apparatus for providing high speed memory for a processing unit

Low latency coherency protocol for a multi-chip multiprocessor system

HOOVER RUSSELL D

Network on chip with an I/O accelerator

Network on chip with a low latency, high bandwidth application messaging interconnect

Context switching in a network on chip by thread saving and restoring pointers to memory arrays containing valid message data

Network on chip with partitions

Graphics processor with snoop filter

Network on chip with caching restrictions for pages of computer memory

Network on chip with caching restrictions for pages of computer memory

BIRAN GIORA

Algorithm engine for use in a pattern matching accelerator

Pattern matching accelerator

Software and hardware managed dual rule bank cache for use in a pattern matching accelerator

Pattern matching engine for use in a pattern matching accelerator

COMPARAN MIGUEL

Network on chip

Low latency variable transfer network communicating variable written to source processing core variable register allocated to destination thread to destination processing core variable register allocated to source thread

Transferring architected state between cores

Allocating cache for use as a dedicated local storage

ADAR ETAI

Sharing sampled instruction address registers for efficient instruction sampling in massively multithreaded processors

HEIL TIMOTHY H

Intelligent cache injection