Inventor

WADE NICHOLAS D

US16 patents

⚠️ This page may combine multiple inventors who share the name “WADE NICHOLAS D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

13 patents

US5606672AFeb 25, 1997

Method and apparatus for multiplexing signals from a bus bridge to an ISA bus interface and an ATA bus interface

INTEL CORP131 citations99

US5822767AOct 13, 1998

Method and apparatus for controlling of a memory subsystem installed with standard page mode memory and an extended data out memory

INTEL CORP34 citations92

US6505282B1Jan 7, 2003

Method and apparatus for determining memory types of a multi-type memory subsystem where memory of the different types are accessed using column control signals with different timing characteristics

INTEL CORP43 citations92

US6393525B1May 21, 2002

Least recently used replacement method with protection

INTEL CORP47 citations92

US5828854AOct 27, 1998

Method and apparatus for multiplexing signals from a bus bridge to an ISA bus interface and an ATA bus interface

INTEL CORP36 citations92

US5818464AOct 6, 1998

Method and apparatus for arbitrating access requests to a shared computer system memory by a graphics controller and memory controller

INTEL CORP35 citations92

US5717873AFeb 10, 1998

Deadlock avoidance mechanism and method for multiple bus topology

INTEL CORP33 citations92

US5625779AApr 29, 1997

Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge

INTEL CORP49 citations92

US6112283AAug 29, 2000

Out-of-order snooping for multiprocessor computer systems

INTEL CORP34 citations91

US6574219B1Jun 3, 2003

Passive message ordering on a decentralized ring

INTEL CORP4 citations61

DIGITAL EQUIPMENT CORP

3 patents

US5404482AApr 4, 1995

Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills

DIGITAL EQUIPMENT CORP208 citations98

US5347648ASep 13, 1994

Ensuring write ordering under writeback cache error conditions

DIGITAL EQUIPMENT CORP188 citations97

US5404483AApr 4, 1995

Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills

DIGITAL EQUIPMENT CORP119 citations96

WADE NICHOLAS D

INTEL CORP

Method and apparatus for multiplexing signals from a bus bridge to an ISA bus interface and an ATA bus interface

Method and apparartus for sharing a signal line between agents

Method and apparatus for sharing a signal line between agents

Scalable cache attributes for an input/output bus

Method and apparatus for controlling of a memory subsystem installed with standard page mode memory and an extended data out memory

Method and apparatus for determining memory types of a multi-type memory subsystem where memory of the different types are accessed using column control signals with different timing characteristics

Least recently used replacement method with protection

Method and apparatus for multiplexing signals from a bus bridge to an ISA bus interface and an ATA bus interface

Method and apparatus for arbitrating access requests to a shared computer system memory by a graphics controller and memory controller

Deadlock avoidance mechanism and method for multiple bus topology

Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge

Out-of-order snooping for multiprocessor computer systems

Passive message ordering on a decentralized ring

DIGITAL EQUIPMENT CORP

Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills

Ensuring write ordering under writeback cache error conditions

Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills