Inventor

YAO LIANG-GI

TW80 patents

⚠️ This page may combine multiple inventors who share the name “YAO LIANG-GI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YAO LIANG-GI

TAIWAN SEMICONDUCTOR MFG

Process for integration of a high dielectric constant gate insulator layer in a CMOS device

Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices

Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices

Methods to create high-k dielectric gate electrodes with backside cleaning

Method and structure for forming high-k gates

Dual-gate structure and method of fabricating integrated circuits having dual-gate structures

Relaxed silicon germanium substrate with low defect density

Process to make high-k transistor dielectrics

Method for reducing interfacial layer thickness for high-k and metal gate stack

Method for treating layers of a gate stack

MOS devices with continuous contact etch stop layer

Epitaxy layer and method of forming the same

Method of making FUSI gate and resulting structure

Relaxed silicon germanium substrate with low defect density

Method for producing low defect density strained -Si channel MOSFETS

Method for producing high throughput strained-Si channel MOSFETS

High-K gate dielectric stack plasma treatment to adjust threshold voltage characteristics

Process to make high-K transistor dielectrics

Epitaxy layer and method of forming the same

Process for integration of a high dielectric constant gate insulator layer in a CMOS device

Method for fabricating laminated silicon gate electrode

Method of forming a novel gate electrode structure comprised of a silicon-germanium layer located between random grained polysilicon layers

Chemical vapor deposition (CVD) method employing wetting pre-treatment

Strained silicon layer fabrication with reduced dislocation defect density

Stress analysis of 3-D structures using tip-enhanced Raman scattering technology

Atomic layer deposition

High-k gate dielectric and method of manufacture

Methods for forming MOS devices with metal-inserted polysilicon gate stack

Process for integration of a high dielectric constant gate insulator layer in a CMOS device

Alignment mark configuration

Method of making an ultrathin silicon dioxide gate with improved dielectric properties using NH3 nitridation and post-deposition rapid thermal annealing

VANGUARD INT SEMICONDUCT CORP

Structure and method for fabricating an interlayer insulating film

Method for improved semiconductor device reliability

Method to make shallow trench isolation structure by HDP-CVD and chemical mechanical polish processes

Method for improving patterning of a conductive layer in an integrated circuit

Etch back method to planarize an interlayer having a critical HDP-CVD deposition process

Anti-reflection oxynitride film for tungsten-silicide substrates

Plasma treatment method for PECVD silicon nitride films for improved passivation layers on semiconductor metal interconnections

Method for fabricating an oxynitride layer having anti-reflective properties and low leakage current

Etch stop layer used for the fabrication of an overlying crown shaped storage node structure

Semiconductor furnace for reducing particulates in a quartz tube and boat

Method for reducing crack of polysilicon in a quartz tube and boat

Method of fabricating a passivation layer for integrated circuits

YAO LIANG-GI

Method for reducing interfacial layer thickness for high-k and metal gate stack

Method for reducing interfacial layer thickness for high-K and metal gate stack

Methods of forming gate dielectric material

LIU KUAN-TING

Multi-layer scavenging metal gate stack for ultra-thin interfacial dielectric layer

TAIWAN SEMICONDUCTOR MFG CO LTD

Method of semiconductor integrated circuit fabrication

YU CHEN-HUA

High-k gate dielectric and method of manufacture

XU JEFF J

Methods and apparatus of fluorine passivation