Inventor

BOHR MARK T

US95 patents

⚠️ This page may combine multiple inventors who share the name “BOHR MARK T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BOHR MARK T

INTEL CORP

Method of making an interposer

Interposer and method of making same

Silicide agglomeration fuse device

Isolation structure formation for semiconductor circuit fabrication

Alternate bump metallurgy bars for power and ground routing

Structure and process flow for fabrication of dual gate floating body integrated MOS transistors

Silicide agglomeration fuse device

Silicide agglomeration device

Self-aligned contacts

Transistor with improved tip profile and method of manufacture thereof

Silicide agglomeration fuse device with notches to enhance programmability

Structure and process flow for fabrication of dual gate floating body integrated MOS transistors

Passivation structure and its method of fabrication

Low damage doping technique for self-aligned source and drain regions

Memory cell design with vertically stacked crossovers

Process for forming contact openings through oxide layers

Techniques for die stacking and associated configurations

Integrated circuit device with back-side interconnection to deep source/drain semiconductor

Channel dopant implantation with automatic compensation for variations in critical dimension

Replacement gates to enhance transistor strain

Interposer and method of making same

Wafer passivation structure and method of fabrication

Self-aligned contact process using low density/low k dielectric

Self-aligned contacts

Penetrating implant for forming a semiconductor device

Transistor with improved tip profile and method of manufacture thereof

On-die de-coupling capacitor using bumps or bars

On-die de-coupling capacitor using bumps or bars and method of making same

Pre-poly emitter implant

CMOS process

CMOS process for fabricating integrated circuits, particularly dynamic memory cells with storage capacitors

Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs

Semiconductor field oxidation process

Self-aligned contacts

Integrated circuit device with crenellated metal trace layout

Hyperchip

Self-aligned contacts

Semiconductor device having tipless epitaxial source/drain regions

Metal on both sides with power distributed through the silicon

Self-aligned contacts

Via blocking layer

Method and apparatus for improved power routing

BOHR MARK T

Semiconductor device having tipless epitaxial source/drain regions

Self-aligned contacts

Self-aligned contacts

Self-aligned contacts

Replacement gates to enhance transistor strain

Semiconductor device having tipless epitaxial source/drain regions

MALLIK DEBENDRA

3D integrated circuit package with window interposer

LEE KEVIN J

3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach