Inventor

MERCHANT SAILESH M

US52 patents

⚠️ This page may combine multiple inventors who share the name “MERCHANT SAILESH M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MERCHANT SAILESH M

AGERE SYSTEMS INC

Reinforced bond pad for a semiconductor device

Solder bump structure for flip chip semiconductor devices and method of manufacture therefore

Integrated circuit device incorporating metallurgical bond to enhance thermal conduction to a heat sink

Reinforced bond pad for a semiconductor device

Junction capacitor structure and fabrication method therefor in a dual damascene process

Semiconductor with damage detection circuitry

Method of eliminating agglomerate particles in a polishing slurry

Test semiconductor device and method for determining Joule heating effects in such a device

Curvilinear chemical mechanical planarization device and method

Method of fabricating a contact with a post contact plug anneal

Microelectronic device layer deposited with multiple electrolytes

Test semiconductor device and method for determining Joule heating effects in such a device

Method of forming metal oxide metal capacitors using multi-step rapid material thermal process and a device formed thereby

Integrated circuit device incorporating metallurigical bond to enhance thermal conduction to a heat sink

Method and structures for testing a semiconductor wafer prior to performing a flip chip bumping process

Method to avoid copper contamination of a via or dual damascene structure

Semiconductor test device with heating circuit

Thermal monitoring and management of integrated circuits

LUCENT TECHNOLOGIES INC

Method of passivating copper interconnects in a semiconductor

DRAM capacitor including Cu plug and Ta barrier and method of forming

Integrated circuit having amorphous silicide layer in contacts and vias and method of manufacture thereof

Barrier layer treatments for tungsten plug

Semiconductor device having aluminum contacts or vias and method of manufacture therefor

Integrated circuit having amorphous silicide layer in contacts and vias and method of manufacture therefor

Semiconductor device having aluminum contacts or vias and method of manufacture therefor

Method of making a semiconductor with copper passivating film

Reducing polish platen corrosion during integrated circuit fabrication

Method of manufacturing semiconductor devices having improved polycide integrity through introduction of a silicon layer within the polycide structure

Method of fabricating aluminum-indium (or thallium) vias for ULSI metallization and interconnects

AGERE SYST GUARDIAN CORP

Capacitor having aluminum alloy bottom plate

Semiconductor device having a metal barrier layer for a dielectric material having a high dielectric constant and a method of manufacture thereof

Tungsten silicide nitride as a barrier for high temperature anneals to improve hot carrier reliability

Diffusion barrier for use with high dielectric constant materials and electronic devices incorporating same

Corrosion-resistant polishing pad conditioner

Metal silicide as a barrier for MOM capacitors in CMOS technologies

Method of fabricating a mom capacitor having a metal silicide barrier

Multi-layered metal silicide resistor for Si Ic&#39;s

Method of eliminating agglomerate particles in a polishing slurry

Method of forming metal oxide metal capacitors using multi-step rapid thermal process and a device formed thereby

PMOS device having a layered silicon gate for improved silicide integrity and enhanced boron penetration resistance

BACHMAN MARK A

Stacked interconnect heat sink

Method of fabrication of through-substrate vias

Integration of shallow trench isolation and through-substrate vias into integrated circuit designs

Solder bump structure for flip chip semiconductor devices and method of manufacturing therefore

LSI CORP

Integration of shallow trench isolation and through-substrate vias into integrated circuit designs

Stacked interconnect heat sink

Preventing electronic device counterfeits

AT & T CORP

Multiple layer tungsten deposition process

Method of forming metal layers formed as a composite of sub-layers using Ti texture control layer

ARCHER III VANCE D

Routing under bond pad for the replacement of an interconnect layer

Multi-layered metal silicide resistor for Si Ic's