Inventor

NEAL DANNY MARVIN

US83 patents

⚠️ This page may combine multiple inventors who share the name “NEAL DANNY MARVIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NEAL DANNY MARVIN

IBM

Error recovery by isolation of peripheral components in a data processing system

Method and apparatus for adding and removing components of a data processing system without powering down

Method and apparatus for reporting unauthorized attempts to access nodes in a network computing system

System area network of end-to-end context via reliable datagram domains

Method and apparatus to perform fabric management

DMA windowing in an LPAR environment using device arbitration level to allow multiple IOAs per terminal bridge

Method and system for reliably defining and determining timeout values in unreliable datagrams

Computer system error recovery and fault isolation

System for determining whether a subsequent transaction may be allowed or must be allowed or must not be allowed to bypass a preceding transaction

Method and system for a merchandise checkout system

Method and system for translating peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a computer system

Secondary I/O bus with expanded slot capacity and hot plugging capability

Method and system for supporting peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a data-processing system

Efficient process for handover between subnet managers

Method and apparatus for ensuring scalable mastership during initialization of a system area network

Method and apparatus for pausing a send queue without causing sympathy errors

Selectively flushing buffered transactions in a bus bridge

Method and system for supporting multiple local buses operating at different frequencies

Bus for high frequency operation with backward compatibility and hot-plug ability

Method and system for supporting peripheral component interconnect (PCI) peer-to-peer access across a PCI host bridge supporting multiple PCI buses

Method and apparatus for improving bus efficiency by enabling arbitration based upon availability of completion data

Method and apparatus for bus arbitration between isochronous and non-isochronous devices

Variable slot configuration for multi-speed bus

Autodocking hardware for installing and/or removing adapter cards without opening the computer system cover

Driver/receiver circuitry for enhanced PCI bus with differential signaling

System and method for simultaneously establishing multiple connections

System, method, and product for managing data transfers in a network

Queue pair resolution in infiniband fabrics

Apparatus and method for virtualizing a queue pair space to minimize time-wait impacts

Method and system for choosing a queue protection key that is tamper-proof from an application

Open format storage subsystem apparatus and method

DMA windowing in an LPAR environment using device arbitration level to allow multiple IOAs per terminal bridge

Enhanced bus arbiter utilizing variable priority and fairness

Transaction routing system

Coherency for DMA read cached data

Device arbitration including peer-to-peer access arbitration

Method and system for interrupt handling using system pipelined packet transfers

System for determining whether a subsequent transaction may be allowed or must be allowed or must not be allowed to bypass a preceding transaction

Method and system for injecting errors to a device within a computer system

Method/system for identifying delayed predetermined information transfer request as bypassable by subsequently-generated information transfer request using bypass enable bit in bridge translation control entry

Dual host bridge with peer to peer support

Voltage overshoot control in hot plug system

Method and system for supporting multiple peripheral component interconnect PCI buses by a single PCI host bridge within a computer system

PCI system and adapter requirements following reset

Enhanced dual speed bus computer system

Method and system for increasing the load and expansion capabilities of a bus through the use of in-line switches

Connector for higher performance PCI with differential signaling

Method and apparatus for improving bus bandwidth by reducing redundant access attempts

System and method for enhancement of system bus to mezzanine bus transactions

ISYS TECHNOLOGIES INC

Transaction credit control for serial I/O systems