Inventor
YANES ADALBERTO GUILLERMO
US26 patents
⚠️ This page may combine multiple inventors who share the name “YANES ADALBERTO GUILLERMO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
25 patentsUS5918242AJun 29, 1999
General-purpose customizable memory controller
IBM64 citations94
US6687240B1Feb 3, 2004
Transaction routing system
IBM26 citations93
US6480917B1Nov 12, 2002
Device arbitration including peer-to-peer access arbitration
IBM23 citations93
US6084934AJul 4, 2000
Natural throttling of data transfer across asynchronous boundaries
IBM52 citations92
US6581129B1Jun 17, 2003
Intelligent PCI/PCI-X host bridge
IBM35 citations91
US6425024B1Jul 23, 2002
Buffer management for improved PCI-X or PCI bridge performance
IBM42 citations90
US5684978ANov 4, 1997
Synchronous DRAM controller with memory access commands timed for optimized use of data bus
IBM23 citations90
US6519718B1Feb 11, 2003
Method and apparatus implementing error injection for PCI bridges
IBM35 citations89
US5687393ANov 11, 1997
System for controlling responses to requests over a data bus between a plurality of master controllers and a slave storage controller by inserting control characters
IBM21 citations87
US6581141B1Jun 17, 2003
Toggle for split transaction mode of PCI-X bridge buffer
IBM15 citations84
US6546447B1Apr 8, 2003
Method and apparatus for dynamic PCI combining for PCI bridges
IBM18 citations84
US6480923B1Nov 12, 2002
Information routing for transfer buffers
IBM19 citations84
US6457077B1Sep 24, 2002
System for executing a current information transfer request even when current information transfer request exceeds current available capacity of a transit buffer
IBM16 citations84
US7734843B2Jun 8, 2010
Computer-implemented method, apparatus, and computer program product for stalling DMA operations during memory migration
IBM15 citations83
US6963990B2Nov 8, 2005
Clock generation for multiple secondary buses of a PCI bridge
IBM13 citations83
US6925086B2Aug 2, 2005
Packet memory system
IBM12 citations81
US6968418B2Nov 22, 2005
Data forwarding by host/PCI-X bridges with buffered packet size determined using system information
IBM15 citations80
US11656792B2May 23, 2023
Mirroring data in write caches of a controller of a non-volatile memory
IBM4 citations75
US6418503B1Jul 9, 2002
Buffer re-ordering system
IBM11 citations74
US6665753B1Dec 16, 2003
Performance enhancement implementation through buffer management/bridge settings
IBM12 citations73
US6957293B2Oct 18, 2005
Split completion performance of PCI-X bridges based on data transfer amount
IBM2 citations63
US11880300B2Jan 23, 2024
Generating multi-plane reads to read pages on planes of a storage die for a page to read
IBM0 citations58
US6766405B2Jul 20, 2004
Accelerated error detection in a bus bridge circuit
IBM1 citations52
US11816046B2Nov 14, 2023
Increased read performance for implementations having multiple interface links
IBM0 citations47
US12204444B2Jan 21, 2025
Increased garbage collection granularity for non-volatile memory
IBM0 citations46