Inventor

NAJAFI ASHTIANI POUYA

CA3 patents

Patents

3 patents

US12423019B2Sep 23, 2025

Read gate training and tracking

ADVANCED MICRO DEVICES INC0 citations53

US12461681B2Nov 4, 2025

Fine-grained clocking and clock distribution in low power double data rate physical layer interface

ADVANCED MICRO DEVICES INC0 citations47

US12585387B2Mar 24, 2026

Clock domain phase adjustment for memory operations

ADVANCED MICRO DEVICES INC0 citations46