Inventor

KALTER HOWARD L

US42 patents

Patents

42 patents

US6440801B1Aug 27, 2002

Structure for folded architecture pillar memory cell

IBM199 citations99

US6114725ASep 5, 2000

Structure for folded architecture pillar memory cell

IBM160 citations99

US5571754ANov 5, 1996

Method of fabrication of endcap chip with conductive, monolithic L-connect for multichip stack

IBM191 citations99

US5563086AOct 8, 1996

Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature

IBM57 citations95

US5058115AOct 15, 1991

Fault tolerant computer memory systems and components employing dual level error correction and detection with lock-up feature

IBM79 citations95

US4782250ANov 1, 1988

CMOS off-chip driver circuits

IBM67 citations95

US5998868ADec 7, 1999

Very dense chip package

IBM45 citations93

US6426904B2Jul 30, 2002

Structures for wafer level test and burn-in

IBM43 citations92

US5972745AOct 26, 1999

Method or forming self-aligned halo-isolated wells

IBM25 citations92

US5581567ADec 3, 1996

Dual level error detection and correction employing data subsets from previously corrected data

IBM33 citations92

US5533036AJul 2, 1996

Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature

IBM36 citations92

US5015880AMay 14, 1991

CMOS driver circuit

IBM27 citations92

US4506341AMar 19, 1985

Interlaced programmable logic array having shared elements

IBM32 citations91

US5031151AJul 9, 1991

Wordline drive inhibit circuit implementing worldline redundancy without an access time penalty

IBM40 citations90

US4363110ADec 7, 1982

Non-volatile dynamic RAM cell

IBM25 citations82

US6429080B2Aug 6, 2002

Multi-level dram trench store utilizing two capacitors and two plates

IBM6 citations74

US6177818B1Jan 23, 2001

Complementary depletion switch body stack off-chip driver

IBM6 citations74

US6177809B1Jan 23, 2001

Redundant input/output driver circuit

IBM7 citations74

US5241500AAug 31, 1993

Method for setting test voltages in a flash write mode

IBM18 citations74

US6730529B1May 4, 2004

Method for chip testing

IBM8 citations73

US6044024AMar 28, 2000

Interactive method for self-adjusted access on embedded DRAM memory macros

IBM10 citations73

US4375085AFeb 22, 1983

Dense electrically alterable read only memory

IBM17 citations73

US5463335AOct 31, 1995

Power up detection circuits

IBM11 citations72

US4566022AJan 21, 1986

Flexible/compressed array macro design

IBM7 citations69

US6369671B1Apr 9, 2002

Voltage controlled transmission line with real-time adaptive control

IBM5 citations63

US4999815AMar 12, 1991

Low power addressing systems

IBM3 citations61

KALTER HOWARD L

Patents

Structure for folded architecture pillar memory cell

Structure for folded architecture pillar memory cell

Method of fabrication of endcap chip with conductive, monolithic L-connect for multichip stack

Integrated memory cube, structure and fabrication

Integrated memory cube structure

Crosstalk-shielded-bit-line dram

Method and apparatus for increasing interchip communications rates

Structures for wafer level test and burn-in

Multichip integrated circuit packages and systems

Method of making shadow RAM cell having a shallow trench EEPROM

Three dimensional multichip package methods of fabrication

Three-dimensional multichip packages and methods of fabrication

Shadow ram cell having a shallow trench eeprom

Dynamic ram with on-chip ecc and optimized bit and word redundancy

Multi-level DRAM trench store utilizing two capacitors and two plates

Method for fabricating a very dense chip package

Very dense integrated circuit package

Stacked double dense read only memory

Method for chip testing

Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature

Fault tolerant computer memory systems and components employing dual level error correction and detection with lock-up feature

CMOS off-chip driver circuits

Very dense chip package

Structures for wafer level test and burn-in

Method or forming self-aligned halo-isolated wells

Dual level error detection and correction employing data subsets from previously corrected data

Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature

CMOS driver circuit

Interlaced programmable logic array having shared elements

Wordline drive inhibit circuit implementing worldline redundancy without an access time penalty

Non-volatile dynamic RAM cell

Multi-level dram trench store utilizing two capacitors and two plates

Complementary depletion switch body stack off-chip driver

Redundant input/output driver circuit

Method for setting test voltages in a flash write mode

Method for chip testing

Interactive method for self-adjusted access on embedded DRAM memory macros

Dense electrically alterable read only memory

Power up detection circuits

Flexible/compressed array macro design

Voltage controlled transmission line with real-time adaptive control

Low power addressing systems