Inventor

ASSADERAGHI FARIBORZ

US77 patents

⚠️ This page may combine multiple inventors who share the name “ASSADERAGHI FARIBORZ”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ASSADERAGHI FARIBORZ

IBM

T-Ram array having a planar cell structure and method for fabricating the same

Mixed memory integration with NVRAM, dram and sram cell structures on same substrate

Process for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and process for forming a new NVRAM cell structure

Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipation

Structure for low cost mixed memory integration, new NVRAM structure, and process for forming the mixed memory and NVRAM structure

Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications

Two-device memory cell on SOI for merged logic and memory applications

Method and system for improving the performance on SOI memory arrays in an SRAM architecture system

Double SOI device with recess etch and epitaxy

Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipation

Grounded body SOI SRAM cell

MOS transistors with raised sources and drains

Low cost mixed memory integration with substantially coplanar gate surfaces

Large value capacitor for SOI

Method of making large value capacitor for SOI

SOI FET design to reduce transient bipolar current

T-RAM cell having a buried vertical thyristor and a pseudo-TFT transfer gate and method for fabricating the same

Memory array with dual wordline operation

SOI transistor with polysilicon seed

SOI CMOS dynamic circuits having threshold voltage control

Pair of FETs including a shared SOI body contact and the method of forming the FETs

Low cost mixed memory integration with FERAM

Method of making low voltage active body semiconductor device

Low voltage active body semiconductor device

Body contact MOSFET

T-RAM array having a planar cell structure and method for fabricating the same

SOI MOSFETS exhibiting reduced floating-body effects

Body contact MOSFET

CMOS structure with non-epitaxial raised source/drain and self-aligned gate and method of manufacture

Integrated circuits with reduced substrate capacitance

Method for use in simulation of an SOI device

SOI-body selective link method and apparatus

Method for use in simulation of an SOI device

Decoupling capacitor structure

Method of building a CMOS structure on thin SOI with source/drain electrodes formed by in situ doped selective amorphous silicon

Soi-body selective link method and apparatus

CMOS structure with maximized polysilicon gate activation and a method for selectively maximizing doping activation in gate, extension, and source/drain regions

RAMBUS INC

Methods and circuits for asymmetric distribution of channel equalization between devices

Methods and circuits for asymmetric distribution of channel equalization between devices

Methods and circuits for asymmetric distribution of channel equalization between devices

Methods and circuits for asymmetric distribution of channel equalization between devices

Methods and circuits for asymmetric distribution of channel equalization between devices

Thermal anneal using word-line heating element

Methods and circuits for asymmetric distribution of channel equalization between devices

INVENSENSE INC

Microelectromechanical systems (MEMS) pressure sensor having a leakage path to a cavity

Systems and apparatus having MEMS acoustic sensors and other MEMS sensors and methods of fabrication of the same

UNIV CALIFORNIA

Dynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation

ZERBE JARED L

Methods and circuits for asymmetric distribution of channel equalization between devices

CHANG KUN-YUNG

Drift cancellation technique for use in clock-forwarding architectures

ALON ELAD

Simultaneous bi-directional link