Inventor

CHEVALLIER CHRISTOPHE J

US222 patents

⚠️ This page may combine multiple inventors who share the name “CHEVALLIER CHRISTOPHE J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEVALLIER CHRISTOPHE J

UNITY SEMICONDUCTOR CORP

Preservation circuit and methods to maintain values representing data in one or more layers of memory

Providing a reference voltage to a cross point memory array

Memory array of a non-volatile ram

Non-volatile memory with a single transistor and resistive memory element

Line drivers that fit within a specified line pitch

Cross point memory array using multiple modes of operation

Cross point memory array using multiple thin films

Preservation circuit and methods to maintain values representing data in one or more layers of memory

Selection device for re-writable memory

Low read current architecture for memory

Layout of driver sets in a cross point memory array

Two terminal memory array having reference cells

Multi-resistive state material that uses dopants

Cross point memory array with fast access time

2-terminal trapped charge memory device with voltage switchable multi-level resistance

Line drivers that use minimal metal layers

Adaptive programming technique for a re-writable conductive memory device

Re-writable memory with non-linear memory element

Cross point memory array with memory plugs exhibiting a characteristic hysteresis

Multiplexor having a reference voltage on unselected lines

Cross point memory array using distinct voltages

Circuits and techniques to compensate data signals for variations of parameters affecting memory cells in cross-point arrays

Multi-resistive state memory device with conductive oxide electrodes

Memory element having islands

Re-writable memory with multiple memory layers

Multi-output multiplexor

MICRON TECHNOLOGY INC

CMOS imager with integrated non-volatile memory

Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure

Timer circuit with programmable decode circuitry

Memory system having flexible architecture and method

Method and circuitry for performing analog over-program and under-program detection for a multistate memory cell

Clock signal from an adjustable oscillator for an integrated circuit

Memory system having flexible architecture and method

Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure

Integrated circuit with temperature detector

Clock signal from an adjustable oscillator for an integrated circuit

Integrated circuit with temperature detector

Clocking scheme and charge transfer switch for increasing the efficiency of a charge pump or other circuit

Memory system having programmable control parameters

Non-volatile memory with test rows for disturb detection

Method for performing analog over-program and under-program detection for a multistate memory cell

Leakage detection in flash memory cell

CMOS imager with integrated circuitry

Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure

Erase verify for non-volatile memory

Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous reading writing or erasure

MICRON QUANTUM DEVICES INC

Apparatus and method for detecting over-programming condition in multistate memory device

Power level detection circuit

Apparatus and method for programming multistate memory device

CHEVALLIER CHRISTOPHE J

CMOS imager with integrated circuitry