Inventor
SANCHETI SANJAY
US7 patents
Patents
7 patentsUS7132854B1Nov 7, 2006
Data path configurable for multiple clocking arrangements
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US7135899B1Nov 14, 2006
System and method for reducing skew in complementary signals that can be used to synchronously clock a double data rate output
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US7113445B1Sep 26, 2006
Multi-port memory cell and access method
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US6100739AAug 8, 2000
Self-timed synchronous pulse generator with test mode
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US7383370B1Jun 3, 2008
Arbiter circuit and signal arbitration method
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US6710636B1Mar 23, 2004
Method and system for high resolution delay lock loop
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US5963487AOct 5, 1999
Write enabling circuitry for a semiconductor memory
CYPRESS SEMICONDUCTOR CORP0 citations50