Inventor

LIN HUAN-JUST

TW126 patents

⚠️ This page may combine multiple inventors who share the name “LIN HUAN-JUST”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIN HUAN-JUST

TAIWAN SEMICONDUCTOR MFG CO LTD

Etch profile control of gate contact opening

Tuning threshold voltage through meta stable plasma treatment

Tuning threshold voltage through meta stable plasma treatment

Vertical device having a protrusion source

Contact for high-k metal gate device

Self-aligned nanowire formation using double patterning

Nano wire structure and method for fabricating the same

Etch profile control of gate contact opening

Vertical device having a protrusion source

Methods of forming a semiconductor device having an air spacer

Tuning threshold voltage through meta stable plasma treatment

Etch profile control of gate contact opening

Self-aligned nanowire formation using double patterning

Vertical device having a protrusion structure

Methods for fabricating vertical-gate-all-around transistor structures

Method of making a silicide beneath a vertical structure

Vertical structure having an etch stop over portion of the source

Method of forming channel of gate structure

Nano wire structure and method for fabricating the same

Fin patterning methods for increased process margin

Selective NFET/PFET recess of source/drain regions

Self-aligned insulated film for high-k metal gate device

Gap patterning for metal-to-source/drain plugs in a semiconductor device

Methods for controlling an end-to-end distance in semiconductor device

Methods for controlling an end-to-end distance in semiconductor device

TAIWAN SEMICONDUCTOR MFG

Method of forming a vertical device

Method of patterning narrow gate electrode

Method using wet etching to trim a critical dimension

Selectively controllable gas feed zones for a plasma reactor

Semiconductor devices with dual-metal gate structures and fabrication methods thereof

Method of forming SOI-like structure in a bulk semiconductor substrate using self-organized atomic migration

Aperture width reduction method for forming a patterned photoresist layer

Dynamic feed forward temperature control to achieve CD etching uniformity

Contact for high-k metal gate device

Semiconductor device and method of forming vertical structure

MOS devices with continuous contact etch stop layer

Method of pull back for forming shallow trench isolation

Method of forming a stacked capacitor structure with increased surface area for a DRAM device

Method of forming a smooth polysilicon surface using a soft etch to enlarge the photo lithography window

Large-scale trimming for ultra-narrow gates

In-situ plasma treatment of advanced resists in fine pattern definition

Method for etching silicon nitride selective to titanium silicide

Method to control gate CD

Method for fabricating a T-shaped hard mask/conductor profile to improve self-aligned contact isolation

Multi-step plasma etch method for plasma etch processing a microelectronic layer

NG JIN-AUN

Self-aligned insulated film for high-k metal gate device

CHUANG HAK-LAY

Contact for high-K metal gate device

LEE SHEN-NAN

High planarizing method for use in a gate last process

YANG JI-YI

Method of forming SOI-like structure in a bulk semiconductor substrate by annealing a lower portion of a trench while protecting an upper portion of the trench

LIU CHIA-CHU

Field effect transistors and method of forming the same