Inventor

YUAN JACK H

US51 patents

⚠️ This page may combine multiple inventors who share the name “YUAN JACK H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YUAN JACK H

SANDISK CORP

Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements

Processing techniques for making a dual floating gate EEPROM cell array

Dual floating gate EEPROM cell array with steering gates shared adjacent cells

Dual floating gate EEPROM cell array with steering gates shared by adjacent cells

Processing techniques for making a dual floating gate EEPROM cell array

Method of making triple polysilicon flash EEPROM arrays having a separate erase gate for each row of floating gates

Low voltage erase of a flash EEPROM system having a common erase electrode for two individual erasable sectors

Method of making dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers

Technique of forming over an irregular surface a polysilicon layer with a smooth surface

Method of making dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with sidewall spacers

Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements

Non-volatile memory cells utilizing substrate trenches

Scalable self-aligned dual floating gate memory cell array and methods of forming the array

Steering gate and bit line segmentation in non-volatile memories

Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming

Dual floating gate EEPROM cell array with steering gates shared by adjacent cells

Method of controlling of floating gate oxide growth by use of an oxygen barrier

Dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers

Low voltage erase of a flash EEPROM system having a common erase electrode for two individually erasable sectors

Scalable self-aligned dual floating gate memory cell array and methods of forming the array

Flash memory array with increased coupling between floating and control gates

Triple polysilicon flash EEPROM arrays having a separate erase gate for each row of floating gates, and methods of manufacturing such arrays

Dense vertical programmable read only memory cell structures and processes for making them

Dense vertical programmable read only memory cell structures and processes for making them

Method of patterning polysilicon layers on substrate

Dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers

Method of making dense vertical programmable read only memory cell structure

Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements

Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements

Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements

Floating gate memory cells utilizing substrate trenches to scale down their size

Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming

Scalable self-aligned dual floating gate memory cell array and methods of forming the array

Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming

Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements

Self-aligned trenches with grown dielectric for high coupling ratio in semiconductor devices

Flash memory array with increased coupling between floating and control gates

Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements

Self-aligned trench filling for narrow gap isolation regions

Memory with self-aligned trenches for narrow gap isolation regions

Methods for self-aligned trench filling with grown dielectric for high coupling ratio in semiconductor devices

Flash memory array with increased coupling between floating and control gates

Non-volatile memory cells utilizing substrate trenches

Method of forming non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors

Scalable self-aligned dual floating gate memory cell array and methods of forming the array

Non-volatile memory cells utilizing substrate trenches

Control of floating gate oxide growth by use of an oxygen barrier

SUNDISK CORP

Dense vertical programmable read only memory cell structures and processes for making them

Dense vertical programmable read only memory cell structure and processes for making them

Method of making dense flash eeprom semiconductor memory structures