Inventor
DRESCHER WOLFRAM
DE25 patents
⚠️ This page may combine multiple inventors who share the name “DRESCHER WOLFRAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SILTECTRA GMBH
15 patentsUS11004723B2May 11, 2021
Wafer production method
SILTECTRA GMBH2 citations73
US10593590B2Mar 17, 2020
Combined wafer production method with laser treatment and temperature-induced stresses
SILTECTRA GMBH2 citations73
US10312135B2Jun 4, 2019
Combined wafer production method with laser treatment and temperature-induced stresses
SILTECTRA GMBH3 citations73
US10978311B2Apr 13, 2021
Method for thinning solid body layers provided with components
SILTECTRA GMBH5 citations72
US10843380B2Nov 24, 2020
Method for the material-saving production of wafers and processing of wafers
SILTECTRA GMBH2 citations72
US11699616B2Jul 11, 2023
Method for producing a layer of solid material
SILTECTRA GMBH0 citations62
US11518066B2Dec 6, 2022
Method of treating a solid layer bonded to a carrier substrate
SILTECTRA GMBH0 citations62
US11201081B2Dec 14, 2021
Method for separating thin layers of solid material from a solid body
SILTECTRA GMBH0 citations62
US12211702B2Jan 28, 2025
Solid body and multi-component arrangement
SILTECTRA GMBH0 citations61
US10229835B2Mar 12, 2019
Splitting method and use of a material in a splitting method
SILTECTRA GMBH0 citations52
US10825732B2Nov 3, 2020
Method of producing stresses in a semiconductor wafer
SILTECTRA GMBH0 citations50
US10580699B1Mar 3, 2020
Method and device for the production of wafers with a pre-defined break initiation point
SILTECTRA GMBH0 citations50
US10304738B2May 28, 2019
Method and device for the production of wafers with a pre-defined break initiation point
SILTECTRA GMBH0 citations50
US10269643B2Apr 23, 2019
Method and device for the production of wafers with a pre-defined break initiation point
SILTECTRA GMBH0 citations50
US10029277B2Jul 24, 2018
Method of producing large-scale layers of solid material
SILTECTRA GMBH0 citations40
NXP BV
4 patentsUS7685439B2Mar 23, 2010
Method for effecting the controlled shutdown of data processing units
NXP BV20 citations92
US7779229B2Aug 17, 2010
Method and arrangement for bringing together data on parallel data paths
NXP BV3 citations62
US7647445B2Jan 12, 2010
Processor bus arrangement
NXP BV4 citations62
US7577818B2Aug 18, 2009
Microprocessor program addressing arrangement having multiple independent complete address generators
NXP BV1 citations48
SYSTEMONIC AG
3 patentsUS7003538B2Feb 21, 2006
Process and apparatus for finite field multiplication (FFM)
SYSTEMONIC AG3 citations61
US6871256B2Mar 22, 2005
Method and arrangement in a stack having a memory segmented into data groups having a plurality of elements
SYSTEMONIC AG3 citations58
US7143211B2Nov 28, 2006
Memory configuration with I/O support
SYSTEMONIC AG0 citations40