Inventor
BRISTOL ROBERT L
US48 patents
⚠️ This page may combine multiple inventors who share the name “BRISTOL ROBERT L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
42 patentsUS8993404B2Mar 31, 2015
Metal-insulator-metal capacitor formation techniques
INTEL CORP92 citations97
US9793163B2Oct 17, 2017
Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects
INTEL CORP28 citations94
US10892223B2Jan 12, 2021
Advanced lithography and self-assembled devices
INTEL CORP11 citations86
US10269623B2Apr 23, 2019
Image tone-reversal with a dielectric using bottom-up cross-linking for back end of line (BEOL) interconnects
INTEL CORP10 citations84
US9932671B2Apr 3, 2018
Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD)
INTEL CORP10 citations84
US9530733B2Dec 27, 2016
Forming layers of materials over small regions by selective chemical reaction including limiting enchroachment of the layers over adjacent regions
INTEL CORP8 citations84
US9005875B2Apr 14, 2015
Pre-patterned hard mask for ultrafast lithographic imaging
INTEL CORP12 citations84
US12218052B2Feb 4, 2025
Advanced lithography and self-assembled devices
INTEL CORP1 citations75
US11854787B2Dec 26, 2023
Advanced lithography and self-assembled devices
INTEL CORP1 citations73
US11594599B2Feb 28, 2023
Quantum dot array devices
INTEL CORP2 citations73
US11373950B2Jun 28, 2022
Advanced lithography and self-assembled devices
INTEL CORP1 citations73
US11320734B2May 3, 2022
Ligand-capped main group nanoparticles as high absorption extreme ultraviolet lithography resists
INTEL CORP2 citations73
US10957844B2Mar 23, 2021
Magneto-electric spin orbit (MESO) structures having functional oxide vias
INTEL CORP3 citations73
US10644113B2May 5, 2020
Quantum dot array devices
INTEL CORP2 citations73
US10615117B2Apr 7, 2020
Self-aligned via
INTEL CORP4 citations73
US10553532B2Feb 4, 2020
Structure and method to self align via to top and bottom of tight pitch metal interconnect layers
INTEL CORP6 citations73
US9553018B2Jan 24, 2017
Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects
INTEL CORP3 citations73
US11137681B2Oct 5, 2021
Lined photobucket structure for back end of line (BEOL) interconnect formation
INTEL CORP2 citations72
US10109583B2Oct 23, 2018
Method for creating alternate hardmask cap interconnect structure with increased overlay margin
INTEL CORP4 citations72
US9443922B2Sep 13, 2016
Metal-insulator-metal capacitor formation techniques
INTEL CORP4 citations72
US11315798B2Apr 26, 2022
Two-stage bake photoresist with releasable quencher
INTEL CORP2 citations70
US9418888B2Aug 16, 2016
Non-lithographically patterned directed self assembly alignment promotion layers
INTEL CORP2 citations63
US11955377B2Apr 9, 2024
Differential hardmasks for modulation of electrobucket sensitivity
INTEL CORP0 citations62
US11874600B2Jan 16, 2024
Ligand-capped main group nanoparticles as high absorption extreme ultraviolet lithography resists
INTEL CORP0 citations62
US11373900B2Jun 28, 2022
Damascene plug and tab patterning with photobuckets
INTEL CORP0 citations62
US11251072B2Feb 15, 2022
Differential hardmasks for modulation of electrobucket sensitivity
INTEL CORP0 citations62
US11069609B2Jul 20, 2021
Techniques for forming vias and other interconnects for integrated circuit structures
INTEL CORP1 citations62
US10892184B2Jan 12, 2021
Photobucket floor colors with selective grafting
INTEL CORP0 citations62
US10867853B2Dec 15, 2020
Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects
INTEL CORP1 citations62
US10804141B2Oct 13, 2020
Damascene plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects
INTEL CORP1 citations62
US11953826B2Apr 9, 2024
Lined photobucket structure for back end of line (BEOL) interconnect formation
INTEL CORP0 citations61
US11955343B2Apr 9, 2024
Two-stage bake photoresist with releasable quencher
INTEL CORP0 citations60
US7332416B2Feb 19, 2008
Methods to manufacture contaminant-gettering materials in the surface of EUV optics
INTEL CORP4 citations60
US11189790B2Nov 30, 2021
Spacer-based patterning for tight-pitch and low-variability random access memory (RAM) bit cells and the resulting structures
INTEL CORP0 citations58
US12012473B2Jun 18, 2024
Directed self-assembly structures and techniques
INTEL CORP0 citations56
US10796909B2Oct 6, 2020
Surface-aligned lithographic patterning approaches for back end of line (BEOL) interconnect fabrication
INTEL CORP0 citations52
US10490416B2Nov 26, 2019
Structures and methods for improved lithographic processing
INTEL CORP0 citations52
US9570349B2Feb 14, 2017
Non-lithographically patterned directed self assembly alignment promotion layers
INTEL CORP0 citations52
US9285682B2Mar 15, 2016
Pre-patterned hard mask for ultrafast lithographic imaging
INTEL CORP0 citations52
US10269622B2Apr 23, 2019
Materials and deposition schemes using photoactive materials for interface chemical control and patterning of predefined structures
INTEL CORP0 citations51
US10457548B2Oct 29, 2019
Integrating MEMS structures with interconnects and vias
INTEL CORP0 citations50
US7825424B2Nov 2, 2010
Methods to manufacture contaminant-gettering materials in the surface of EUV optics
INTEL CORP0 citations50
BRISTOL ROBERT L
3 patentsUS9041217B1May 26, 2015
Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects
BRISTOL ROBERT L53 citations97
US9406512B2Aug 2, 2016
Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects
BRISTOL ROBERT L16 citations92
US9236342B2Jan 12, 2016
Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects
BRISTOL ROBERT L21 citations92