Inventor

CHAWLA JASMEET S

US19 patents

⚠️ This page may combine multiple inventors who share the name “CHAWLA JASMEET S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHAWLA JASMEET S

INTEL CORP

Method and structure to contact tight pitch conductive layers with guided vias using alternating hardmasks and encapsulating etchstop liner scheme

Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches

Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches

Transistors with metal source and drain contacts including a Heusler alloy

Semiconductor devices with metal contacts including crystalline alloys

Magneto-electric spin orbit (MESO) structures having functional oxide vias

Microelectronic conductive routes and methods of making the same

Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches

Methods for forming interconnect layers having tight pitch interconnect structures

Maskless air gap to prevent via punch through

Method for creating alternate hardmask cap interconnect structure with increased overlay margin

Techniques for forming vias and other interconnects for integrated circuit structures

Maskless air gap to prevent via punch through

Self-aligned via below subtractively patterned interconnect

Compliant layer for wafer to wafer bonding

MYERS ALAN M

Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects

Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects

JEZEWSKI CHRISTOPHER J

Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches

TAHOE RES LTD

Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches