P

Inventor

SCHENKER RICHARD E

US39 patents
⚠️ This page may combine multiple inventors who share the name “SCHENKER RICHARD E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

37 patents
US9793163B2Oct 17, 2017

Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects

INTEL CORP28 citations94
US10892223B2Jan 12, 2021

Advanced lithography and self-assembled devices

INTEL CORP11 citations86
US11437283B2Sep 6, 2022

Backside contacts for semiconductor devices

INTEL CORP12 citations85
US10937689B2Mar 2, 2021

Self-aligned hard masks with converted liners

INTEL CORP7 citations84
US10032643B2Jul 24, 2018

Method and structure to contact tight pitch conductive layers with guided vias using alternating hardmasks and encapsulating etchstop liner scheme

INTEL CORP16 citations84
US12218052B2Feb 4, 2025

Advanced lithography and self-assembled devices

INTEL CORP1 citations75
US11996411B2May 28, 2024

Stacked forksheet transistors

INTEL CORP4 citations74
US6428936B1Aug 6, 2002

Method and apparatus that compensates for phase shift mask manufacturing defects

INTEL CORP7 citations74
US11854787B2Dec 26, 2023

Advanced lithography and self-assembled devices

INTEL CORP1 citations73
US11373950B2Jun 28, 2022

Advanced lithography and self-assembled devices

INTEL CORP1 citations73
US11011463B2May 18, 2021

Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication and structures resulting therefrom

INTEL CORP3 citations73
US10553532B2Feb 4, 2020

Structure and method to self align via to top and bottom of tight pitch metal interconnect layers

INTEL CORP6 citations73
US9659860B2May 23, 2017

Method and structure to contact tight pitch conductive layers with guided vias

INTEL CORP2 citations73
US9553018B2Jan 24, 2017

Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects

INTEL CORP3 citations73
US9379010B2Jun 28, 2016

Methods for forming interconnect layers having tight pitch interconnect structures

INTEL CORP4 citations73
US11239112B2Feb 1, 2022

Passivating silicide-based approaches for conductive via fabrication and structures resulting therefrom

INTEL CORP3 citations72
US10109583B2Oct 23, 2018

Method for creating alternate hardmask cap interconnect structure with increased overlay margin

INTEL CORP4 citations72
US9312204B2Apr 12, 2016

Methods of forming parallel wires of different metal materials through double patterning and fill techniques

INTEL CORP3 citations67
US12087594B2Sep 10, 2024

Colored gratings in microelectronic structures

INTEL CORP0 citations62
US12080639B2Sep 3, 2024

Contact over active gate structures with metal oxide layers to inhibit shorting

INTEL CORP1 citations62
US11990403B2May 21, 2024

Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication and structures resulting therefrom

INTEL CORP0 citations62
US11610810B2Mar 21, 2023

Maskless air gap enabled by a single damascene process

INTEL CORP0 citations62
US11605623B2Mar 14, 2023

Materials and layout design options for DSA on transition regions over active die

INTEL CORP0 citations62
US11373900B2Jun 28, 2022

Damascene plug and tab patterning with photobuckets

INTEL CORP0 citations62
US10867853B2Dec 15, 2020

Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects

INTEL CORP1 citations62
US10804141B2Oct 13, 2020

Damascene plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects

INTEL CORP1 citations62
US10546772B2Jan 28, 2020

Self-aligned via below subtractively patterned interconnect

INTEL CORP1 citations62
US12237223B2Feb 25, 2025

Contact over active gate structures using directed self-assembly for advanced integrated circuit structure fabrication

INTEL CORP0 citations60
US12087836B2Sep 10, 2024

Contact over active gate structures with metal oxide-caped contacts to inhibit shorting

INTEL CORP0 citations60
US12080605B2Sep 3, 2024

Backside contacts for semiconductor devices

INTEL CORP1 citations60
US11972979B2Apr 30, 2024

1D vertical edge blocking (VEB) via and plug

INTEL CORP0 citations60
US11837644B2Dec 5, 2023

Contact over active gate structures with metal oxide-caped contacts to inhibit shorting

INTEL CORP0 citations60
US11721580B2Aug 8, 2023

1D vertical edge blocking (VEB) via and plug

INTEL CORP0 citations60
US12293913B1May 6, 2025

Directed self-assembly enabled subtractive metal patterning

INTEL CORP0 citations57
US12012473B2Jun 18, 2024

Directed self-assembly structures and techniques

INTEL CORP0 citations56
US12154855B2Nov 26, 2024

Self-aligned patterning with colored blocking and structures resulting therefrom

INTEL CORP0 citations51
US10770291B2Sep 8, 2020

Methods and masks for line end formation for back end of line (BEOL) interconnects and structures resulting therefrom

INTEL CORP0 citations42

BRISTOL ROBERT L

1 patent

TAHOE RES LTD

1 patent