Inventor
DAMARAJU SATISH
US14 patents
Patents
14 patentsUS6845432B2Jan 18, 2005
Low power cache architecture
INTEL CORP44 citations92
US7136984B2Nov 14, 2006
Low power cache architecture
INTEL CORP23 citations89
US7130236B2Oct 31, 2006
Low power delay controlled zero sensitive sense amplifier
INTEL CORP17 citations83
US7457917B2Nov 25, 2008
Reducing power consumption in a sequential cache
INTEL CORP11 citations80
US7689772B2Mar 30, 2010
Power-performance modulation in caches using a smart least recently used scheme
INTEL CORP11 citations78
US10473718B2Nov 12, 2019
Multibit vectored sequential with scan
INTEL CORP4 citations72
US11442103B2Sep 13, 2022
Multibit vectored sequential with scan
INTEL CORP0 citations62
US11398814B2Jul 26, 2022
Low-power single-edge triggered flip-flop, and time borrowing internally stitched flip-flop
INTEL CORP1 citations62
US11009549B2May 18, 2021
Multibit vectored sequential with scan
INTEL CORP0 citations62
US12543594B2Feb 3, 2026
Scalable package architecture using reticle stitching and photonics for integrated circuits
INTEL CORP0 citations58
US12541476B2Feb 3, 2026
Chiplet architecture for late bind SKU fungibility
INTEL CORP0 citations52
US8356202B2Jan 15, 2013
System and method for reducing power consumption in a device using register files
INTEL CORP1 citations47
US12436467B2Oct 7, 2025
Simulating die rotation to minimize area overhead of reticle stitching for stacked dies
INTEL CORP0 citations46
US7805619B2Sep 28, 2010
Circuit technique to reduce leakage during reduced power mode
INTEL CORP0 citations31