Inventor
BUENNING HARTMUT
DE12 patents
⚠️ This page may combine multiple inventors who share the name “BUENNING HARTMUT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
NXP BV
11 patentsUS9196537B2Nov 24, 2015
Protection of a wafer-level chip scale package (WLCSP)
NXP BV6 citations82
US8987057B2Mar 24, 2015
Encapsulated wafer-level chip scale (WLSCP) pedestal packaging
NXP BV8 citations82
US9847258B2Dec 19, 2017
Plasma dicing with blade saw patterned underside mask
NXP BV16 citations81
US9601437B2Mar 21, 2017
Plasma etching and stealth dicing laser process
NXP BV7 citations81
US8809166B2Aug 19, 2014
High die strength semiconductor wafer processing method and system
NXP BV9 citations81
US9245804B2Jan 26, 2016
Using a double-cut for mechanical protection of a wafer-level chip scale package (WLCSP)
NXP BV4 citations71
US8895363B2Nov 25, 2014
Die preparation for wafer-level chip scale package (WLCSP)
NXP BV3 citations58
US9812361B2Nov 7, 2017
Combination grinding after laser (GAL) and laser on-off function to increase die strength
NXP BV1 citations49
US9349645B2May 24, 2016
Apparatus, device and method for wafer dicing
NXP BV0 citations48
US10410922B2Sep 10, 2019
Semiconductor device with six-sided protected walls
NXP BV0 citations40
US10347534B2Jul 9, 2019
Variable stealth laser dicing process
NXP BV0 citations38