Inventor
MANNAVA PHANINDRA K
US19 patents
⚠️ This page may combine multiple inventors who share the name “MANNAVA PHANINDRA K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
15 patentsUS7313712B2Dec 25, 2007
Link power saving state
INTEL CORP71 citations98
US7610500B2Oct 27, 2009
Link power saving state
INTEL CORP17 citations92
US7600080B1Oct 6, 2009
Avoiding deadlocks in a multiprocessor system
INTEL CORP45 citations91
US7016304B2Mar 21, 2006
Link level retry scheme
INTEL CORP25 citations90
US7738484B2Jun 15, 2010
Method, system, and apparatus for system level initialization
INTEL CORP8 citations84
US7836144B2Nov 16, 2010
System and method for a 3-hop cache coherency protocol
INTEL CORP10 citations82
US7991875B2Aug 2, 2011
Link level retry scheme
INTEL CORP10 citations81
US7953902B2May 31, 2011
Negotiable exchange of link layer functional parameters in electronic systems having components interconnected by a point-to-point network
INTEL CORP2 citations62
US9148485B2Sep 29, 2015
Reducing packet size in a communication protocol
INTEL CORP2 citations61
US8898393B2Nov 25, 2014
Optimized ring protocols and techniques
INTEL CORP1 citations60
US7831776B2Nov 9, 2010
Dynamic allocation of home coherency engine tracker resources in link based computing system
INTEL CORP2 citations56
US7937505B2May 3, 2011
Method and system for flexible and negotiable exchange of link layer functional parameters
INTEL CORP0 citations52
US7328368B2Feb 5, 2008
Dynamic interconnect width reduction to improve interconnect availability
INTEL CORP0 citations52
US7320094B2Jan 15, 2008
Retraining derived clock receivers
INTEL CORP1 citations52
US9392062B2Jul 12, 2016
Optimized ring protocols and techniques
INTEL CORP0 citations49