Inventor

DING WEIQI

US78 patents

⚠️ This page may combine multiple inventors who share the name “DING WEIQI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DING WEIQI

ALTERA CORP

Signal loss detector for high-speed serial interface of a programmable logic device

System and method for receiver equalization adaptation

Transmitter with multiple phase locked loops

High-frequency low-gain ring VCO for clock-data recovery in high-speed serial interface of a programmable logic device

High-speed charge pump circuits

Interposer with embedded clock network circuitry

Methods and apparatus for multiple-stage CTLE adaptation

Method and apparatus for receiver VGA adaptation

Methods and apparatus for decision feedback equalization adaptation

Input-output circuitry for integrated circuits

Apparatus and methods for on-die instrumentation

Configurable emphasis for high-speed transmitter driver circuitry

Phase interpolator circuits and methods

Signal detect for high-speed serial interface

Methods and apparatus for performing runtime data eye monitoring and continuous data strobe calibration

Clock data recovery circuitry with programmable clock phase selection

Programmable high-speed voltage-mode differential driver

Methods and apparatus for clock tree phase alignment

Integrated circuit device with field programmable optical array

Systems and methods for reducing power supply noise or jitter

Techniques for level shifting signals

High-speed signal detect for serial interface

Integrated circuit architectures with heterogeneous high-speed serial interface circuitry

Phase-locked loop architecture and clock distribution system

Reference clock architecture for integrated circuit device

Methods and apparatus for performing bit swapping in clock data recovery circuitry

DING WEIQI

On-chip eye viewer architecture for highspeed transceivers

Apparatus and methods for detection and correction of transmitter duty cycle distortion

Techniques for configuring multi-path feedback loops

On-chip full eye viewer architecture

Analog signal test circuits and methods

Shielded metal-oxide-metal (MOM) capacitor structure

Apparatus and methods for transmitter output swing calibration

Apparatus and methods for transceiver power adaptation

Techniques for reducing duty cycle distortion in periodic signals

High-speed differential comparator circuitry with accurately adjustable threshold

On-chip data signal eye monitoring circuitry and methods

Serial data signal eye width estimator methods and apparatus

Equalizer circuitry with selectable tap positions and coefficients

Integrated circuits with configurable inductors

Flexible receiver architecture

LI WEI

Methods and apparatus for calibrating pipeline analog-to-digital converters

Systems and methods for digital calibration of successive-approximation-register analog-to-digital converter

PHAM TIEN DUC

Phase-locked loop architecture and clock distribution system

ATESOGLU ALI

Latched comparator circuitry

PAN MINGDE

Multi-level amplitude signaling receiver

CHAN ALLEN

PLD architecture optimized for 10G Ethernet physical layer solution

NGUYEN TOAN THANH

Multiple channel bonding in a high speed clock network

LI PENG

Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations

TRAN THUNGOC M

High-speed serial data signal interface circuitry with multi-data-rate switching capability