Inventor

COMPARAN MIGUEL

US33 patents

⚠️ This page may combine multiple inventors who share the name “COMPARAN MIGUEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

COMPARAN MIGUEL

MICROSOFT TECHNOLOGY LICENSING LLC

No miss cache structure for real-time image transformations with data compression

No miss cache structure for real-time image transformations with multiple LSR processing engines

Selective application of reprojection processing on layer sub-regions for optimizing late stage reprojection power

Post-rendering image transformation using parallel image transformation pipelines

No miss cache structure for real-time image transformations with multiple LSR processing engines

No miss cache structure for real-time image transformations

Methods and systems for multistage post-rendering image transformation

No miss cache structure for real-time image transformations with data compression

Interfacing with superconducting circuitry

Reducing negative effects of insufficient data throughput for real-time processing

Reducing negative effects of insufficient data throughput for real-time processing

Selectively applying reprojection processing to multi-layer scenes for optimizing late stage reprojection power

COMPARAN MIGUEL

Anisotropic texture filtering with texture data prefetching

Anisotropic texture filtering with texture data prefetching

Method and apparatus for executing instructions

Network on chip

Low latency variable transfer network communicating variable written to source processing core variable register allocated to destination thread to destination processing core variable register allocated to source thread

Transferring architected state between cores

Hard memory array failure recovery utilizing locking structure

Dynamic data type aligned cache optimized for misaligned packed structures

Near neighbor data cache sharing

Allocating cache for use as a dedicated local storage

IBM

Network on chip that maintains cache coherency with invalidate commands

Network on chip that maintains cache coherency with invalidate commands

Allocating cache for use as a dedicated local storage

Near neighbor data cache sharing

Processing unit incorporating L1 cache bypass

Processor with hybrid pipeline capable of operating in out-of-order and in-order modes

Processor with hybrid pipeline capable of operating in out-of-order and in-order modes

Transferring architected state between cores

Processor with hybrid pipeline capable of operating in out-of-order and in-order modes

BROWN JEFFREY D

Multi-core processor with internal voting-based built in self test (BIST)

MUMFORD CLINT WAYNE

Test and characterization of ring in superconducting domain through built-in self-test