Inventor

MEJDRICH ERIC O

US58 patents

⚠️ This page may combine multiple inventors who share the name “MEJDRICH ERIC O”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MEJDRICH ERIC O

MEJDRICH ERIC O

Performance event triggering through direct interthread communication on a network on chip

Software pipelining on a network on chip

Single step mode in a software pipeline within a highly threaded network on a chip microprocessor

Instruction buffer bypass of target instruction in response to partial flush

Software pipelining on a network on chip

DMA-based acceleration of command push buffer between host and target devices

Parallelized ray tracing

Multithreaded software rendering pipeline with dynamic performance-based reallocation of raster threads

Propagating shared state changes to multiple threads within a multithreaded processing environment

Sequential processing in network on chip nodes by threads generating message containing payload and pointer for nanokernel to access algorithm to be executed on payload in another node

Rolling texture context data structure for maintaining texture data in a multithreaded image processing pipeline

Parallelized streaming accelerated data structure generation

Multithreaded physics engine with predictive load balancing

Allocating resources based on a performance statistic

Emulating a computer run time environment

Vector register file caching of context data structure for maintaining state data in a multithreaded image processing pipeline

Network on chip that maintains cache coherency with invalidation messages

Multithreaded physics engine with impulse propagation

Security methodology to prevent user from compromising throughput in a highly threaded network on a chip processor

IBM

Dynamic virtual software pipelining on a network on chip

Network on chip with low latency, high bandwidth application messaging interconnects that abstract hardware inter-thread data communications into an architected state of a processor

Multiple spacial indexes for dynamic scene management in graphics rendering

Pixel color accumulation in a ray tracing image processing system

Network on chip with an I/O accelerator

Monitoring software pipeline performance on a network on chip

Network on chip that maintains cache coherency with invalidate commands

Network on chip that maintains cache coherency with invalidate commands

Network on chip with a low latency, high bandwidth application messaging interconnect

System and method for transfer of data between processors using a locked set, head and tail pointers

Snoop filter directory mechanism in coherency shared memory system

Graphics rendering on a network on chip

Preferential dispatching of computer program instructions

Recovering data from a plurality of packets

Software debugger for packets in a network on a chip

Network on chip with partitions

Direct access of cache lock set data without backing memory

HOOVER RUSSELL D

Network on chip with an I/O accelerator

Network on chip with a low latency, high bandwidth application messaging interconnect

Context switching in a network on chip by thread saving and restoring pointers to memory arrays containing valid message data

Network on chip with partitions

Graphics processor with snoop filter

Network on chip with caching restrictions for pages of computer memory

FOWLER DAVID K

Accelerated data structure optimization based upon view orientation

Physical rendering with textured bounding volume primitive mapping

Accelerated data structure positioning based upon view orientation

COMPARAN MIGUEL

Network on chip

MICROSOFT CORP

Secure privilege level execution and access protection

SCHARDT PAUL E

Reuse of static image data from prior image frames to reduce rasterization requirements

MICROSOFT TECHNOLOGY LICENSING LLC

Modular computing device with common AC power

HICKEY MARK J

Programmable integrated processor blocks