Inventor
DOBBS CARL S
US39 patents
⚠️ This page may combine multiple inventors who share the name “DOBBS CARL S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
COHERENT LOGIX INC
35 patentsUS9990241B2Jun 5, 2018
Processing system with interspersed processors with multi-layer interconnection
COHERENT LOGIX INC20 citations94
US9430369B2Aug 30, 2016
Memory-network processor with programmable optimizations
COHERENT LOGIX INC20 citations92
US8963599B2Feb 24, 2015
Multi-frequency clock skew control for inter-chip communication in synchronous digital systems
COHERENT LOGIX INC13 citations91
US9720867B2Aug 1, 2017
Processing system with interspersed processors with multi-layer interconnection
COHERENT LOGIX INC3 citations84
US9612984B2Apr 4, 2017
Multiprocessor system with improved secondary interconnection network
COHERENT LOGIX INC6 citations84
US9424213B2Aug 23, 2016
Processing system with interspersed processors DMA-FIFO
COHERENT LOGIX INC4 citations84
US9292464B2Mar 22, 2016
Multiprocessor system with improved secondary interconnection network
COHERENT LOGIX INC7 citations84
US9450590B2Sep 20, 2016
Clock distribution network for multi-frequency multi-processor systems
COHERENT LOGIX INC4 citations82
US9154142B2Oct 6, 2015
Multi-frequency clock skew control for inter-chip communication in synchronous digital systems
COHERENT LOGIX INC6 citations82
US10838787B2Nov 17, 2020
Processing system with interspersed processors with multi-layer interconnect
COHERENT LOGIX INC2 citations73
US11544072B2Jan 3, 2023
Memory-network processor with programmable optimizations
COHERENT LOGIX INC2 citations72
US11483580B2Oct 25, 2022
Distributed architecture for encoding and delivering video content
COHERENT LOGIX INC4 citations72
US9323714B2Apr 26, 2016
Processing system with synchronization instruction
COHERENT LOGIX INC3 citations72
US10747709B2Aug 18, 2020
Memory network processor
COHERENT LOGIX INC1 citations71
US10007293B2Jun 26, 2018
Clock distribution network for multi-frequency multi-processor systems
COHERENT LOGIX INC2 citations71
US9430422B2Aug 30, 2016
Processing system with interspersed processors with multi-layer interconnect
COHERENT LOGIX INC2 citations63
US9424441B2Aug 23, 2016
Multiprocessor fabric having configurable communication that is selectively disabled for secure processing
COHERENT LOGIX INC1 citations63
US12306773B2May 20, 2025
Multiprocessor system with improved secondary interconnection network
COHERENT LOGIX INC0 citations62
US12197970B2Jan 14, 2025
Processing system with interspersed processors DMA-FIFO
COHERENT LOGIX INC0 citations62
US11900124B2Feb 13, 2024
Memory-network processor with programmable optimizations
COHERENT LOGIX INC0 citations62
US11755504B2Sep 12, 2023
Multiprocessor system with improved secondary interconnection network
COHERENT LOGIX INC0 citations62
US11030023B2Jun 8, 2021
Processing system with interspersed processors DMA-FIFO
COHERENT LOGIX INC0 citations62
US11016779B2May 25, 2021
Memory-network processor with programmable optimizations
COHERENT LOGIX INC0 citations62
US9325329B2Apr 26, 2016
Automatic selection of on-chip clock in synchronous digital systems
COHERENT LOGIX INC1 citations61
US11829320B2Nov 28, 2023
Memory network processor
COHERENT LOGIX INC0 citations60
US11550750B2Jan 10, 2023
Memory network processor
COHERENT LOGIX INC0 citations60
US11327753B2May 10, 2022
Processor instructions to accelerate FEC encoding and decoding
COHERENT LOGIX INC0 citations59
US10747689B2Aug 18, 2020
Multiprocessor system with improved secondary interconnection network
COHERENT LOGIX INC0 citations52
US10685143B2Jun 16, 2020
Secure boot sequence for selectively disabling configurable communication paths of a multiprocessor fabric
COHERENT LOGIX INC0 citations52
US10521285B2Dec 31, 2019
Processing system with interspersed processors with multi-layer interconnection
COHERENT LOGIX INC0 citations52
US10185608B2Jan 22, 2019
Processing system with interspersed processors with multi-layer interconnection
COHERENT LOGIX INC0 citations52
US10185672B2Jan 22, 2019
Multiprocessor system with improved secondary interconnection network
COHERENT LOGIX INC0 citations52
US10007806B2Jun 26, 2018
Secure boot sequence for selectively disabling configurable communication paths of a multiprocessor fabric
COHERENT LOGIX INC0 citations52
US9558150B2Jan 31, 2017
Processing system with synchronization instruction
COHERENT LOGIX INC0 citations51
US10691451B2Jun 23, 2020
Processor instructions to accelerate FEC encoding and decoding
COHERENT LOGIX INC0 citations49