Inventor

KULKARNI PRANITA

US94 patents

⚠️ This page may combine multiple inventors who share the name “KULKARNI PRANITA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KULKARNI PRANITA

CHENG KANGGUO

Three dimensional FET devices having different device widths

Integrated circuit including DRAM and SRAM/logic

CMOS structure having multiple threshold voltage devices

SOI device with DTI and STI

Stressed Fin-FET devices with low contact resistance

Raised source/drain structure for enhanced strain coupling from stress liner

Stressed Fin-FET devices with low contact resistance

Method of forming extremely thin semiconductor on insulator (ETSOI) device without ion implantation

Isolation in CMOSFET devices utilizing buried air bags

MOSFET with work function adjusted metal backgate

Raised source/drain structure for enhanced strain coupling from stress liner

Junctionless transistor

MOSFET with recessed channel film and abrupt junctions

Formation of embedded stressor through ion implantation

Integrated circuit diode

CMOS structure having multiple threshold voltage devices

Semiconductor devices with raised extensions

Implant free extremely thin semiconductor devices

Device and method of reducing junction leakage

Semiconductor structure having NFET extension last implants

Semiconductor structure having NFET and PFET formed in SOI substrate with underlapped extensions

DORIS BRUCE B

Shallow trench isolation structures

Inversion mode varactor

SOI trench DRAM structure with backside strap

Strained thin body CMOS device having vertically raised source/drain stressors with single spacer

Same-chip multicharacteristic semiconductor structures

Shallow trench isolation structures

IBM

Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same

Controlled fin-merging for fin type FET devices

Strained thin body semiconductor-on-insulator substrate and device

ANDO TAKASHI

FinFET parasitic capacitance reduction using air gap

FinFET parasitic capacitance reduction using air gap

BEDELL STEPHEN W

Strained devices, methods of manufacture and design structures

Strained thin body semiconductor-on-insulator substrate and device

GLOBALFOUNDRIES INC

Methods of forming a semiconductor device with a protected gate cap layer and the resulting device

Methods of forming a semiconductor device with a protected gate cap layer and the resulting device

CAI MING

Embedded stressors for multigate transistor devices

Tensile stress enhancement of nitride film for stressed channel field effect transistor fabrication

ADAM THOMAS N

Semiconductor structure having NFET extension last implants

Semiconductor substrate with transistors having different threshold voltages

CAI JIN

Integrated circuit having back gating, improved isolation and reduced well resistance and method to fabricate same

KHAKIFIROOZ ALI

Local interconnect structure self-aligned to gate structure

NING TAK H

Junction field effect transistor with an epitaxially grown gate structure

WONG KEITH KWONG HON

Integrated circuit with replacement metal gates and dual dielectrics

GUO DECHAO

Stressor in planar field effect transistor device

HAENSCH WILFRIED ERNST-AUGUST

Structure and method to fabricate resistor on finFET processes

HAENSCH WILFRIED E

FinFET-compatible metal-insulator-metal capacitor

BERLINER NATHANIEL C

Method to enable compressively strained pFET channel in a FinFET structure by implant and thermal diffusion

ONTALUS VIOREL

Source and drain doping profile control employing carbon-doped semiconductor material

KULKARNI PRANITA

FinFET device having reduce capacitance, access resistance, and contact resistance