Inventor

YEH TSE-YU

US42 patents

⚠️ This page may combine multiple inventors who share the name “YEH TSE-YU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YEH TSE-YU

INTEL CORP

System for processing a cluster of instructions where the instructions are issued to the execution units having a priority order according to a template associated with the cluster of instructions

Method and apparatus for performing reads of related data from a set-associative cache memory

Method and apparatus for performing early branch prediction in a microprocessor

Method and apparatus for branch prediction using first and second level branch prediction tables

Validating prediction for branches in a cluster via comparison of predicted and condition selected tentative target addresses and validation of branch conditions

Optimized branch predictions for strongly predicted compiler branches

Microcode upgrade and special function support by executing RISC instruction to invoke resident microcode

Processor and instruction set with predict instructions

Return address predictor that uses branch instructions to track a last valid return address

Method and apparatus for generating branch predictions for multiple branch instructions indexed by a single instruction pointer

Predicate controlled software pipelined loop processing with prediction of predicate writing and value prediction for use in subsequent iteration

Method and apparatus for predicting loop exit branches

Apparatus and method for cycle accounting in microprocessors

Decentralized exception processing system

Apparatus and method for cycle accounting in microprocessors

Branch prediction table having pointers identifying other branches within common instruction cache lines

Processor executing plural instruction sets (ISA&#39;s) with ability to have plural ISA&#39;s in different pipeline stages at same time

Microprocessor having a branch predictor using speculative branch registers

Target instructions prefetch cache

Electronic system and method for maintaining synchronization of multiple front-end pipelines

BROADCOM CORP

Power consumption reduction in a pipeline by stalling instruction issue on a load miss

Inhibiting of a co-issuing instruction in a processor having different pipeline lengths

Comparing operands of instructions against a replay scoreboard to detect an instruction replay and copying a replay scoreboard to an issue scoreboard

Mechanism for processing speclative LL and SC instructions in a pipelined processor

Mechanism for processing speculative LL and SC instructions in a pipelined processor

Limiting performance in an integrated circuit to meet export restrictions

APPLE INC

L1 cache flush when processor is entering low power mode

Combining write buffer with dynamically adjustable flush metrics

Efficient encoding for detecting load dependency on store with misalignment

Replay reduction for power saving

Efficient encoding for detecting load dependency on store with misalignment

Combining write buffer with dynamically adjustable flush metrics

INST THE DEV OF EMERGING ARCHI

Dynamic branch prediction for branch instructions with multiple targets

Instruction prefetch mechanism utilizing a branch predict instruction

Processor with apparatus for tracking prefetch and demand fetch instructions serviced by cache memory

High-performance processor with streaming buffer that facilitates prefetching of instructions

IDEA CORP

Method for processing branch operations

Instruction template for efficient processing clustered branch instructions

YEH TSE-YU

Misalignment predictor

Misalignment predictor

KELLER JAMES B

L1 flush mechanism to flush cache for power down and handle coherence during flush and/or after power down

CHANG PO-YUNG

Replay reduction for power saving

Processor executing plural instruction sets (ISA's) with ability to have plural ISA's in different pipeline stages at same time