Inventor
PARANJPE AJIT
US13 patents
⚠️ This page may combine multiple inventors who share the name “PARANJPE AJIT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
VEECO INSTR INC
6 patentsUS6572744B1Jun 3, 2003
Dual collimated deposition apparatus and method of use
VEECO INSTR INC16 citations91
US9978934B2May 22, 2018
Ion beam etching of STT-RAM structures
VEECO INSTR INC10 citations78
US9356188B2May 31, 2016
Tensile separation of a semiconducting stack
VEECO INSTR INC5 citations72
US12104242B2Oct 1, 2024
Deposition system with integrated carrier cleaning modules
VEECO INSTR INC0 citations51
US9938621B2Apr 10, 2018
Methods of wafer processing with carrier extension
VEECO INSTR INC1 citations49
US9761671B2Sep 12, 2017
Engineered substrates for use in crystalline-nitride based devices
VEECO INSTR INC0 citations48
APPLIED MATERIALS INC
4 patentsUS7713881B2May 11, 2010
Process sequence for doped silicon fill of deep trenches
APPLIED MATERIALS INC16 citations92
US7446366B2Nov 4, 2008
Process sequence for doped silicon fill of deep trenches
APPLIED MATERIALS INC15 citations92
US7109097B2Sep 19, 2006
Process sequence for doped silicon fill of deep trenches
APPLIED MATERIALS INC14 citations92
US7354848B2Apr 8, 2008
Poly-silicon-germanium gate stack and method for forming the same
APPLIED MATERIALS INC8 citations69