Inventor
JAYANTI SRIKANT
US17 patents
⚠️ This page may combine multiple inventors who share the name “JAYANTI SRIKANT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MICRON TECHNOLOGY INC
11 patentsUS9275909B2Mar 1, 2016
Methods of fabricating semiconductor structures
MICRON TECHNOLOGY INC17 citations91
US8946807B2Feb 3, 2015
3D memory
MICRON TECHNOLOGY INC25 citations91
US9559109B2Jan 31, 2017
Memory including blocking dielectric in etch stop tier
MICRON TECHNOLOGY INC5 citations84
US9064970B2Jun 23, 2015
Memory including blocking dielectric in etch stop tier
MICRON TECHNOLOGY INC11 citations84
US10170639B2Jan 1, 2019
3D memory
MICRON TECHNOLOGY INC10 citations83
US10103160B2Oct 16, 2018
Semiconductor structures including dielectric materials having differing removal rates
MICRON TECHNOLOGY INC8 citations83
US9230986B2Jan 5, 2016
3D memory
MICRON TECHNOLOGY INC13 citations83
US10170491B2Jan 1, 2019
Memory including blocking dielectric in etch stop tier
MICRON TECHNOLOGY INC2 citations73
US11063059B2Jul 13, 2021
Semiconductor structures including dielectric materials having differing removal rates
MICRON TECHNOLOGY INC3 citations72
US11889693B2Jan 30, 2024
Semiconductor devices including stack oxide materials having different densities or different oxide portions, and semiconductor devices including stack dielectric materials having different portions
MICRON TECHNOLOGY INC0 citations61
US10847527B2Nov 24, 2020
Memory including blocking dielectric in etch stop tier
MICRON TECHNOLOGY INC0 citations52
INTEL CORP
5 patentsUS9412821B2Aug 9, 2016
Stacked thin channels for boost and leakage improvement
INTEL CORP15 citations91
US9209199B2Dec 8, 2015
Stacked thin channels for boost and leakage improvement
INTEL CORP25 citations91
US10290642B2May 14, 2019
Flash memory devices incorporating a polydielectric layer
INTEL CORP2 citations70
US10903219B2Jan 26, 2021
Method for making a flash memory device
INTEL CORP0 citations60
US10622450B2Apr 14, 2020
Modified floating gate and dielectric layer geometry in 3D memory arrays
INTEL CORP1 citations59