Inventor
CHAO CLINTON
US29 patents
⚠️ This page may combine multiple inventors who share the name “CHAO CLINTON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG
16 patentsUS7576435B2Aug 18, 2009
Low-cost and ultra-fine integrated circuit packaging technique
TAIWAN SEMICONDUCTOR MFG255 citations99
US7427803B2Sep 23, 2008
Electromagnetic shielding using through-silicon vias
TAIWAN SEMICONDUCTOR MFG84 citations97
US7880278B2Feb 1, 2011
Integrated circuit having stress tuning layer
TAIWAN SEMICONDUCTOR MFG10 citations92
US7514775B2Apr 7, 2009
Stacked structures and methods of fabricating stacked structures
TAIWAN SEMICONDUCTOR MFG24 citations92
US7494846B2Feb 24, 2009
Design techniques for stacking identical memory dies
TAIWAN SEMICONDUCTOR MFG42 citations92
US7112522B1Sep 26, 2006
Method to increase bump height and achieve robust bump structure
TAIWAN SEMICONDUCTOR MFG25 citations92
US7804177B2Sep 28, 2010
Silicon-based thin substrate and packaging schemes
TAIWAN SEMICONDUCTOR MFG31 citations91
US7795735B2Sep 14, 2010
Methods for forming single dies with multi-layer interconnect structures and structures formed therefrom
TAIWAN SEMICONDUCTOR MFG30 citations90
US8367474B2Feb 5, 2013
Method of manufacturing integrated circuit having stress tuning layer
TAIWAN SEMICONDUCTOR MFG6 citations84
US8945998B2Feb 3, 2015
Programmable semiconductor interposer for electronic package and method of forming
TAIWAN SEMICONDUCTOR MFG15 citations83
US7812426B2Oct 12, 2010
TSV-enabled twisted pair
TAIWAN SEMICONDUCTOR MFG14 citations83
US7565635B2Jul 21, 2009
SiP (system in package) design systems and methods
TAIWAN SEMICONDUCTOR MFG9 citations80
US7696766B2Apr 13, 2010
Ultra-fine pitch probe card structure
TAIWAN SEMICONDUCTOR MFG2 citations61
US7642793B2Jan 5, 2010
Ultra-fine pitch probe card structure
TAIWAN SEMICONDUCTOR MFG2 citations61
US9275948B2Mar 1, 2016
Integrated circuit having stress tuning layer
TAIWAN SEMICONDUCTOR MFG0 citations52
US7977155B2Jul 12, 2011
Wafer-level flip-chip assembly methods
TAIWAN SEMICONDUCTOR MFG1 citations51
TAIWAN SEMICONDUCTOR MFG CO LTD
4 patentsUS11935842B2Mar 19, 2024
Methods of manufacturing an integrated circuit having stress tuning layer
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations73
US11094646B2Aug 17, 2021
Methods of manufacturing an integrated circuit having stress tuning layer
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations73
US10269730B2Apr 23, 2019
Methods of manufacturing an integrated circuit having stress tuning layer
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations73
US9633954B2Apr 25, 2017
Methods of manufacturing an integrated circuit having stress tuning layer
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations73