Inventor
FORTIN GUILLAUME
CA22 patents
⚠️ This page may combine multiple inventors who share the name “FORTIN GUILLAUME”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CADENCE DESIGN SYSTEMS INC
11 patentsUS9831874B1Nov 28, 2017
Tunable impedance circuit for a transmitter output stage
CADENCE DESIGN SYSTEMS INC19 citations89
US11356304B1Jun 7, 2022
Quarter-rate data sampling with loop-unrolled decision feedback equalization
CADENCE DESIGN SYSTEMS INC10 citations83
US10547298B1Jan 28, 2020
Duty cycle correction system and method
CADENCE DESIGN SYSTEMS INC18 citations82
US10355889B1Jul 16, 2019
Adaptive pattern filtering for clock and data recovery to minimize interaction with decision feedback equalization
CADENCE DESIGN SYSTEMS INC6 citations72
US11469769B1Oct 11, 2022
Data sampler with capacitive digital-to-analog converter
CADENCE DESIGN SYSTEMS INC2 citations70
US11323117B1May 3, 2022
Data sampling with loop-unrolled decision feedback equalization
CADENCE DESIGN SYSTEMS INC3 citations70
US11381208B1Jul 5, 2022
Continuous time linear equalization system and method
CADENCE DESIGN SYSTEMS INC3 citations64
US9964593B1May 8, 2018
Boundary scan receiver
CADENCE DESIGN SYSTEMS INC4 citations62
US11736230B1Aug 22, 2023
Digitally-controlled quadrature correction loop
CADENCE DESIGN SYSTEMS INC1 citations59
US10225115B1Mar 5, 2019
Low-frequency periodic signal detector
CADENCE DESIGN SYSTEMS INC1 citations58
US9705499B1Jul 11, 2017
System and method for interchangeable transmission driver output stage and low-power margining mode
CADENCE DESIGN SYSTEMS INC1 citations48
PMC SIERRA INC
7 patentsUS7969195B1Jun 28, 2011
Active biasing in metal oxide semiconductor (MOS) differential pairs
PMC SIERRA INC17 citations92
US7471107B1Dec 30, 2008
Active biasing in metal oxide semiconductor (MOS) differential pairs
PMC SIERRA INC31 citations92
US7738617B1Jun 15, 2010
Clock and data recovery locking technique for large frequency offsets
PMC SIERRA INC17 citations88
US7884660B2Feb 8, 2011
Variable-length digitally-controlled delay chain with interpolation-based tuning
PMC SIERRA INC11 citations84
US7733149B2Jun 8, 2010
Variable-length digitally-controlled delay chain with interpolation-based tuning
PMC SIERRA INC10 citations84
US9325305B1Apr 26, 2016
Active biasing in metal oxide semiconductor (MOS) differential pairs
PMC SIERRA INC1 citations62
US8018251B1Sep 13, 2011
Input/output interfacing with low power
PMC SIERRA INC2 citations62