P

Inventor

OTT JOHN A

US65 patents
⚠️ This page may combine multiple inventors who share the name “OTT JOHN A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

39 patents
US6350993B1Feb 26, 2002

High speed composite p-channel Si/SiGe heterostructure for field effect devices

IBM404 citations98
US6858502B2Feb 22, 2005

High speed composite p-channel Si/SiGe heterostructure for field effect devices

IBM39 citations95
US7705345B2Apr 27, 2010

High performance strained silicon FinFETs device and method for forming same

IBM52 citations93
US9000594B2Apr 7, 2015

Use of graphene to limit copper surface oxidation, diffusion and electromigration in interconnect structures

IBM16 citations92
US7999251B2Aug 16, 2011

Nanowire MOSFET with doped epitaxial contacts for source and drain

IBM22 citations92
US9812530B2Nov 7, 2017

High germanium content silicon germanium fins

IBM6 citations84
US9761661B2Sep 12, 2017

Stacked strained and strain-relaxed hexagonal nanowires

IBM6 citations84
US9739728B1Aug 22, 2017

Automatic defect detection and classification for high throughput electron channeling contrast imaging

IBM16 citations84
US9741532B1Aug 22, 2017

Multi-beam electron microscope for electron channeling contrast imaging of semiconductor material

IBM10 citations84
US9680018B2Jun 13, 2017

Method of forming high-germanium content silicon germanium alloy fins on insulator

IBM7 citations84
US9608160B1Mar 28, 2017

Polarization free gallium nitride-based photonic devices on nanopatterned silicon

IBM19 citations84
US9530643B2Dec 27, 2016

Selective epitaxy using epitaxy-prevention layers

IBM5 citations84
US9496263B1Nov 15, 2016

Stacked strained and strain-relaxed hexagonal nanowires

IBM9 citations84
US9406529B1Aug 2, 2016

Formation of FinFET junction

IBM10 citations84
US9324843B2Apr 26, 2016

High germanium content silicon germanium fins

IBM8 citations84
US9058990B1Jun 16, 2015

Controlled spalling of group III nitrides containing an embedded spall releasing plane

IBM8 citations84
US7785939B2Aug 31, 2010

Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers

IBM9 citations84
US7521376B2Apr 21, 2009

Method of forming a semiconductor structure using a non-oxygen chalcogen passivation treatment

IBM10 citations84
US9306107B2Apr 5, 2016

Buffer layer for high performing and low light degraded solar cells

IBM10 citations83
US10902912B2Jan 26, 2021

Electrochemical switching device with protective encapsulation

IBM2 citations73
US10460937B2Oct 29, 2019

Post growth heteroepitaxial layer separation for defect reduction in heteroepitaxial films

IBM2 citations73
US9947533B2Apr 17, 2018

Selective epitaxy using epitaxy-prevention layers

IBM2 citations73
US9859091B1Jan 2, 2018

Automatic alignment for high throughput electron channeling contrast imaging

IBM2 citations73
US9553153B1Jan 24, 2017

Post growth defect reduction for heteroepitaxial materials

IBM4 citations73
US8691608B2Apr 8, 2014

Semiconductor devices having nanochannels confined by nanometer-spaced electrodes

IBM2 citations63
US8053330B2Nov 8, 2011

Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide

IBM2 citations63
US11003942B2May 11, 2021

Electron channeling pattern acquisition from small crystalline areas

IBM0 citations62
US10833311B2Nov 10, 2020

Method of making an anode structure containing a porous region

IBM1 citations62
US7084431B2Aug 1, 2006

High speed composite p-channel Si/SiGe heterostructure for field effect devices

IBM3 citations62
US7405422B2Jul 29, 2008

Epitaxial and polycrystalline growth of Si1-x-yGexCy and Si1-yCy alloy layers on Si by UHV-CVD

IBM2 citations60
US10840433B2Nov 17, 2020

MRAM with high-aspect ratio bottom electrode

IBM0 citations52
US10755925B2Aug 25, 2020

Post growth heteroepitaxial layer separation for defect reduction in heteroepitaxial films

IBM0 citations52
US10658513B2May 19, 2020

Formation of FinFET junction

IBM0 citations52
US10453683B2Oct 22, 2019

Post growth heteroepitaxial layer separation for defect reduction in heteroepitaxial films

IBM0 citations52
US10417519B2Sep 17, 2019

Electron channeling pattern acquisition from small crystalline areas

IBM0 citations52
US10388522B2Aug 20, 2019

Selective epitaxy using epitaxy-prevention layers

IBM0 citations52
US10236384B2Mar 19, 2019

Formation of FinFET junction

IBM0 citations52
US10127649B2Nov 13, 2018

Electron channeling pattern acquisition from small crystalline areas

IBM0 citations52
US10109737B2Oct 23, 2018

Method of forming high-germanium content silicon germanium alloy fins on insulator

IBM0 citations52

BONILLA GRISELDA

2 patents

OTT JOHN A

2 patents

SAMSUNG ELECTRONICS CO LTD

1 patent

BEDELL STEPHEN W

1 patent

DE SOUZA JOEL P

1 patent

YIN HAIZHOU

1 patent

CHU JACK O

1 patent

HARRER STEFAN

1 patent

DIMITRAKOPOULOS CHRISTOS D

1 patent

Showing the top 50 of 65 patents by PatentIndex Score.