Inventor

PEY KIN LEONG

SG39 patents

⚠️ This page may combine multiple inventors who share the name “PEY KIN LEONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PEY KIN LEONG

CHARTERED SEMICONDUCTOR MFG

Dual metal gate process: metals and their silicides

Method of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistance

Methods to form dual metal gates by incorporating metals and their conductive oxides

Salicide formation on narrow poly lines by pulling back of spacer

Silicon nitride--TEOS oxide, salicide blocking layer for deep sub-micron devices

Dual metal gate process: metals and their silicides

Activating source and drain junctions and extensions using a single laser anneal

Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing process

Dual metal gate process: metals and their silicides

Methods to form dual metal gates by incorporating metals and their conductive oxides

Formation of silicided shallow junctions using implant through metal technology and laser annealing process

Salicide method for producing a semiconductor device using silicon/amorphous silicon/metal structure

Method to reduce variation in LDD series resistance

Method to reduce polysilicon depletion in MOS transistors

Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication

Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide process

In-line process monitoring using micro-raman spectroscopy

Method to form MOS transistors with shallow junctions using laser annealing

Cmos gate architecture for integration of salicide process in sub 0.1 . .muM devices

Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctions

Ultra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS application

Incorporation of dielectric layer onto SThM tips for direct thermal analysis

Integrated circuit system using dual damascene process

Methods to form dual metal gates by incorporating metals and their conductive oxides

Method of forming dual thickness gate dielectric structures via use of silicon nitride layers

Methods for effective nickel silicide formation

Method and apparatus for performing nickel salicidation

Method and apparatus for performing nickel salicidation

Methods to form dual metal gates by incorporating metals and their conductive oxides

Selective CVD TiSi2 deposition with TiSi2 liner

Selective CVD TiSi2 deposition with TiSi2 liner

GLOBALFOUNDRIES SG PTE LTD

Control gate dummy for word line uniformity and method for producing the same

Formation of strained Si channel and Si1-xGex source/drain structures using laser annealing

RRAM cell with bottom electrode(s) positioned in a semiconductor substrate

TAN DEXTER XUEMING

Low OHMIC contacts

Method for fabricating semiconductor devices with shallow diffusion regions

TAN DEXTER

Method for fabricating nano devices

UNIV NANYANG TECH

Method for forming a shallow junction region using defect engineering and laser annealing

LIM YEOW KHENG

Slot designs in wide metal lines