Inventor

MEARS ROBERT J

US92 patents

⚠️ This page may combine multiple inventors who share the name “MEARS ROBERT J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MEARS ROBERT J

RJ MEARS LLC

Integrated circuit comprising a waveguide having an energy band engineered superlattice

Method for making a semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel

Method for making an integrated circuit comprising a waveguide having an energy band engineered superlattice

Method for making a semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structure

Method for making semiconductor device including band-engineered superlattice

Semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structure

Semiconductor device including band-engineered superlattice

Semiconductor device including band-engineered superlattice

Semiconductor device including band-engineered superlattice

Semiconductor device including MOSFET having band-engineered superlattice

Semiconductor device including band-engineered superlattice

Method for making semiconductor device including band-engineered superlattice

Method for making semiconductor device including band-engineered superlattice

Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction

Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction

Semiconductor device including a superlattice with regions defining a semiconductor junction

Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction

Optical filter device with aperiodically arranged grating elements

Method for making semiconductor device including band-engineered superlattice

MEARS TECHNOLOGIES INC

Electronic device comprising active optical devices with an energy band engineered superlattice

Semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel

Integrated circuit comprising an active optical device having an energy band engineered superlattice

Semiconductor device including MOSFET having band-engineered superlattice

Multiple-wavelength opto-electronic device including a superlattice

Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures

Semiconductor device including a strained superlattice layer above a stress layer

Semiconductor device including a strained superlattice and overlying stress layer and related methods

Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions

Method for making a multiple-wavelength opto-electronic device including a superlattice

Semiconductor device comprising a lattice matching layer

Method for making a semiconductor device comprising a lattice matching layer

Methods of making spintronic devices with constrained spintronic dopant

Method for making an electronic device including a poled superlattice having a net electrical dipole moment

Method for making a semiconductor device comprising a superlattice dielectric interface layer

ATOMERA INC

Semiconductor device including resonant tunneling diode structure having a superlattice

CMOS image sensor including superlattice to enhance infrared light absorption

Method for making a semiconductor device including a resonant tunneling diode structure having a superlattice

Semiconductor devices with enhanced deterministic doping and related methods

Semiconductor device including a resonant tunneling diode structure with electron mean free path control layers

Method for making a semiconductor device including a resonant tunneling diode with electron mean free path control layers

Method of making a semiconductor device with a buried insulating layer formed by annealing a superlattice

Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods

Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods

Semiconductor device including a superlattice and replacement metal gate structure and related methods

Semiconductor device including superlattice structures with reduced defect densities

Method for making a varactor with hyper-abrupt junction region including a superlattice

Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistance

Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistance

MEARS ROBERT J

Multiple-wavelength opto-electronic device including a superlattice

NAT RES DEV

Fabrication of optical fibers