Inventor

BLANKENSHIP ROBERT G

US104 patents

⚠️ This page may combine multiple inventors who share the name “BLANKENSHIP ROBERT G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BLANKENSHIP ROBERT G

INTEL CORP

Transmitting peer-to-peer transactions through a coherent interface

Multichip package link error detection

Multichip package link

High performance interconnect

High performance interconnect physical layer

High performance interconnect physical layer

Separating transactions into different virtual channels

High performance interconnect

Method and system for performing data movement operations with read snapshot and in place write update

Multiple transaction data flow control unit for high-speed interconnect

High performance interconnect physical layer

High performance interconnect link layer

Multislot link layer flit wherein flit includes three or more slots whereby each slot comprises respective control field and respective payload field

High performance interconnect physical layer

Speculative reads in buffered memory

Two level memory full line writes

Providing common caching agent for core and integrated input/output (IO) module

Atomic operations in PCI express

High performance interconnect link layer

Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory

Fast deskew when exiting low-power partial-width high speed link state

PCI express transaction descriptor

Transaction re-ordering

Prefectching in PCI express

Globally unique transaction identifiers

High performance interconnect

Error handling in transactional buffered memory

High performance interconnect

Method and system for performing data movement operations with read snapshot and in place write update

Multichip package link

Method and apparatus for the synchronization of distributed caches

Multi-node chipset lock flow with peer-to-peer non-posted I/O requests

Method and apparatus for the synchronization of distributed caches

Method and apparatus for initiating CPU data prefetches by an external agent

Methods and arrangements to enhance an upbound path

Multichip package link error detection

Multichip package link error detection

High performance interconnect physical layer

Multichip package link error detection

High performance interconnect physical layer

High performance interconnect physical layer

Implied directory state updates

Early identification in transactional buffered memory

Control messaging in multislot link layer flit

IYER VENKATRAMAN

Embedded control channel for high speed serial interconnect

Enhanced interconnect link width modulation for power savings

SAFRANEK ROBERT J

Multiple transaction data flow control unit for high-speed interconnect

LIU YEN-CHENG

Providing common caching agent for core and integrated input/output (IO) module

BLANKENSHIP ROBERT G

Ring protocol for low latency interconnect switch

WILLEY JEFF

Multislot link layer flit wherein flit includes three or more slots whereby each slot comprises respective control field and respective payload field