Inventor
SWANSON JEFFREY C
US32 patents
⚠️ This page may combine multiple inventors who share the name “SWANSON JEFFREY C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
22 patentsUS9626321B2Apr 18, 2017
High performance interconnect
INTEL CORP14 citations92
US9355058B2May 31, 2016
High performance interconnect physical layer
INTEL CORP13 citations92
US12197357B2Jan 14, 2025
High performance interconnect
INTEL CORP2 citations85
US10360098B2Jul 23, 2019
High performance interconnect link layer
INTEL CORP4 citations84
US10204064B2Feb 12, 2019
Multislot link layer flit wherein flit includes three or more slots whereby each slot comprises respective control field and respective payload field
INTEL CORP5 citations84
US9444492B2Sep 13, 2016
High performance interconnect link layer
INTEL CORP6 citations84
US11741030B2Aug 29, 2023
High performance interconnect
INTEL CORP2 citations83
US10248591B2Apr 2, 2019
High performance interconnect
INTEL CORP5 citations83
US9740646B2Aug 22, 2017
Early identification in transactional buffered memory
INTEL CORP4 citations73
US9740654B2Aug 22, 2017
Control messaging in multislot link layer flit
INTEL CORP2 citations73
US9507746B2Nov 29, 2016
Control messaging in multislot link layer flit
INTEL CORP3 citations73
US12189550B2Jan 7, 2025
High performance interconnect
INTEL CORP0 citations72
US11269793B2Mar 8, 2022
High performance interconnect
INTEL CORP0 citations72
US10061719B2Aug 28, 2018
Packed write completions
INTEL CORP5 citations72
US10146733B2Dec 4, 2018
High performance interconnect physical layer
INTEL CORP1 citations63
US9479196B2Oct 25, 2016
High performance interconnect link layer
INTEL CORP2 citations63
US9208121B2Dec 8, 2015
High performance interconnect physical layer
INTEL CORP2 citations63
US10198379B2Feb 5, 2019
Early identification in transactional buffered memory
INTEL CORP1 citations62
US10365965B2Jul 30, 2019
High performance interconnect link layer
INTEL CORP0 citations52
US10140240B2Nov 27, 2018
Control messaging in multislot link layer flit
INTEL CORP0 citations52
US9537665B2Jan 3, 2017
Method, apparatus, and system for enabling platform power states
INTEL CORP0 citations51
US12541460B2Feb 3, 2026
Memory transaction queue bypass based on configurable address and bandwidth conditions
INTEL CORP0 citations50
HEWLETT PACKARD DEVELOPMENT CO
7 patentsUS7325164B2Jan 29, 2008
System and method for multiple cycle capture of chip state
HEWLETT PACKARD DEVELOPMENT CO20 citations92
US6662313B1Dec 9, 2003
System and method for multiple cycle capture of chip state
HEWLETT PACKARD DEVELOPMENT CO32 citations92
US6594714B1Jul 15, 2003
Reconfigurable FIFO interface to support multiple channels in bundled agent configurations
HEWLETT PACKARD DEVELOPMENT CO36 citations92
US6591332B1Jul 8, 2003
Apparatus and method for tracking flushes of cache entries in a data processing system
HEWLETT PACKARD DEVELOPMENT CO13 citations84
US6775640B1Aug 10, 2004
Performance adder for tracking occurrence of events within a circuit
HEWLETT PACKARD DEVELOPMENT CO11 citations74
US6587965B1Jul 1, 2003
System and method for single point observability of a dual-mode control interface
HEWLETT PACKARD DEVELOPMENT CO7 citations74
US7480590B2Jan 20, 2009
Performance adder for tracking occurrence of events within a circuit
HEWLETT PACKARD DEVELOPMENT CO2 citations63