Inventor

SAFRANEK ROBERT J

US61 patents

⚠️ This page may combine multiple inventors who share the name “SAFRANEK ROBERT J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SAFRANEK ROBERT J

INTEL CORP

Multichip package link

Partially inclusive snoop filter

High performance interconnect

High performance interconnect

Multiple transaction data flow control unit for high-speed interconnect

High performance interconnect link layer

Multislot link layer flit wherein flit includes three or more slots whereby each slot comprises respective control field and respective payload field

High performance interconnect link layer

High performance interconnect

High performance interconnect

Multichip package link

Cross-die interface snoop or global observation message ordering

NoDMA cache

High performance interconnect

High performance interconnect

High performance interconnect coherence protocol resolving conflict based on home transaction identifier different from requester transaction identifier

Multichip package link

High performance interconnect link layer

Techniques for entering a low-power link state

Techniques for entering a low-power link state

Reducing packet size in a communication protocol

Multiple transaction data flow control unit for high-speed interconnect

High performance interconnect link layer

AT & T BELL LAB

Adaptive non-linear quantizer

Hdtv encoder with forward estimation and constant rate motion vectors

Hdtv receiver

High definition television coding arrangement with graceful degradation

Image processing system

Adaptive leak hdtv encoder

High definition television arrangement with signal selections adapted to the available transmission capacity

High definition television arrangement employing motion compensated prediction error signals

Television signal arrangement where selected signals are encoded digitally

Adaptive leak HDTV encoder

HDTV receiver

IBM

Multiprocessor computer system with memory map translation

Directory tree multinode computer system

Maintaining order of write operations in a multiprocessor for memory consistency

Method for invalidating cache lines on a sharing list

SAFRANEK ROBERT J

Multiple transaction data flow control unit for high-speed interconnect

Implementing quickpath interconnect protocol over a PCIe interface

Raw memory transaction support

SEQUENT COMPUTER SYSTEMS INC

Method and apparatus for maintaining an order of write operations by processors in a multiprocessor computer to maintain memory consistency

Distributed shared memory system having a first node that prevents other nodes from accessing requested data until a processor on the first node controls the requested data

BEERS ROBERT H

Satisfying memory ordering requirements between partial reads and non-snoop accesses

Satisfying memory ordering requirements between partial reads and non-snoop accesses

AT & T CORP

Perceptually-adapted image coding system

LUCENT TECHNOLOGIES INC

Compression of signals for perceptual quality by selecting frequency bands having relatively high energy

CHANG LUKE

Tunneling platform management messages through inter-processor interconnects

WILLEY JEFF

Multislot link layer flit wherein flit includes three or more slots whereby each slot comprises respective control field and respective payload field

MANNAVA PHANINDRA K

Generating a packet including multiple operation codes