Inventor

WU ZUOGUO

US55 patents

⚠️ This page may combine multiple inventors who share the name “WU ZUOGUO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WU ZUOGUO

INTEL CORP

Multichip package link error detection

Reduced jitter amplification methods and apparatuses

Inverter based duty cycle correction apparatuses and systems

Adaptive termination for optimum signal detection

Multichip package link

Method, apparatus, system for centering in a high performance interconnect

Die-to-die interconnect

Multichip package link error detection

Integrated circuit package with test circuitry for testing a channel between dies

Multichip package link error detection

Multichip package link error detection

High performance repeater

Linear resistor with high resolution and bandwidth

High performance optical repeater

Frequency multiplying delay-locked loop

Extending multichip package link off package

High performance interconnect

PCI express enhancements

Multichip package link

High performance interconnect

Standard interfaces for die to die (D2D) interconnect stacks

Compliance and debug testing of a die-to-die interconnect

Optical IO interconnect having a WDM architecture and CDR clock sharing receiver

Data receiver including a transconductance amplifier

On-package die-to-die (D2D) interconnect for memory using universal chiplet interconnect express (UCIe) PHY

Retimers to extend a die-to-die interconnect

Valid signal for latency sensitive die-to-die (D2D) interconnects

Extending multichip package link off package

Skew detection and compensation for high speed I/O links

Clock-gating in die-to-die (D2D) interconnects

PHY-based retry techniques for die-to-die interfaces

Extending multichip package link off package

Extending multichip package link off package

Discrete circuit having cross-talk noise cancellation circuitry and method thereof

Approximate data bus inversion technique for latency sensitive applications

Characterization of transmission media

Valid lane training

PCI express enhancements

PCI express enhancements

Voltage modulated control lane

Lane repair and lane reversal implementation for die-to-die (D2D) interconnects

Link initialization training and bring up for die-to-die interconnect

Sideband interface for die-to-die interconnects

Apparatus, method, and system for performing error correction based on laser power setting

Near field wireless communication system for mother to package and package to package sideband digital communication

Connector with active circuit

Automated detection of high performance interconnect coupling

WU ZUOGUO

Input/output driver swing control and supply noise rejection

Differential circuit with offset control

HINCK TODD A

Interconnection of a packaged chip to a die in a package utilizing on-package input/output interfaces