Inventor

HOEI JUNG SHENG

US127 patents

⚠️ This page may combine multiple inventors who share the name “HOEI JUNG SHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOEI JUNG SHENG

MICRON TECHNOLOGY INC

Non-equal threshold voltage ranges in MLC NAND

M+N bit programming and M+L bit read for M bit memory cells

Memory devices with read level calibration

Analog sensing of memory cells in a solid state memory device

Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device

Memory controller self-calibration for removing systemic influence

Analog sensing of memory cells with a source follower driver in a semiconductor memory device

Programming sequence in NAND memory

Non-volatile multilevel memory cells with data read of reference cells

Program window adjust for memory cell signal line delay

M+L bit read column architecture for M bit memory cells

NAND temperature data management

NAND temperature data management

Redundant array of independent NAND for a three-dimensional memory array

Memory controller self-calibration for removing systemic influence

Analog sensing of memory cells with a source follower driver in a semiconductor memory device

Memory adapted to program a number of bits to a memory cell and read a different number of bits from the memory cell

Methods for segmented programming and memory devices

Configurable digital and analog input/output interface in a memory device

Analog-to-digital and digital-to-analog conversion window adjustment based on reference cells in a memory device

Temperature sensitive NAND programming

Sensing memory cells

Memory controller self-calibration for removing systemic influence

Memory controller self-calibration for removing systemic influence

Non-volatile multilevel memory cells with data read of reference cells

M+N bit programming and M+L bit read for M bit memory cells

Memory access collision management on a shared wordline

Memory device virtual blocks using half good blocks

Automatic wordline status bypass management

Memory access collision management on a shared wordline

Memory sub-system management of firmware block record and device block record

NAND temperature data management

Methods of error-based read disturb mitigation and memory devices utilizing the same

SARIN VISHAL

Apparatus having a string of memory cells

Memory device program window adjustment

M+N bit programming and M+L bit read for M bit memory cells

Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device

Reducing noise in semiconductor devices

Non-volatile multilevel memory cells with data read of reference cells

Soft landing for desired program threshold voltage

ROOHPARVAR FRANKIE F

Refresh of non-volatile memory cells based on fatigue conditions

Refresh of non-volatile memory cells based on fatigue conditions

INFORMATION STORAGE DEVICES

Method and apparatus for automatic gain control using a linear limiter circuit with voltage controlled resistors as a variable element

AC coupling and signal amplification using switched capacitors

HOEI JUNG-SHENG

Methods of operating memories including characterizing memory cell signal lines

Memory cell sensing device equipped with a ramp voltage generator using a digital-to-analog converter (DAC) and counters, and sensing methods thereof

RADKE WILLIAM H

Data conditioning to improve flash memory reliability

LSI LOGIC CORP

Automatic delay matching circuit for data serializer

HELM MARK

Three dimensional memory control circuitry

INTEL CORP

Three dimensional memory control circuitry