Inventor

FELIX NELSON

US50 patents

⚠️ This page may combine multiple inventors who share the name “FELIX NELSON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FELIX NELSON

IBM

Patterning material film stack with metal-containing top coat for enhanced sensitivity in extreme ultraviolet (EUV) lithography

Bottom source/drain etch with fin-cut-last-VTFET

Boundary protection for CMOS multi-threshold voltage devices

Wet strippable OPL using reversible UV crosslinking and de-crosslinking

Patterning material film stack with metal-containing top coat for enhanced sensitivity in extreme ultraviolet (EUV) lithography

Litho-etch-litho-etch with self-aligned blocks

Dynamic adjustment of post exposure bake during lithography utilizing real-time feedback for wafer exposure delay

Dielectric reflow for boundary control

Enabling residue free gap fill between nanosheets

Enabling residue free gap fill between nanosheets

Bottom source/drain etch with fin-cut-last-VTFET

Polymer brush adhesion promoter with UV cleavable linker

Inverse tone pillar printing method using organic planarizing layer pillars

Bottom source/drain etch with fin-cut-last-VTFET

EUV pattern transfer using graded hardmask

Fabrication of back-end-of-line interconnects

Patterning material film stack with hard mask layer configured to support selective deposition on patterned resist layer

Semiconductor structure with fully aligned vias

Line break repairing layer for extreme ultraviolet patterning stacks

Polymer brush adhesion promoter with UV cleavable linker

Patterning material film stack with metal-containing top coat for enhanced sensitivity in extreme ultraviolet (EUV) lithography

Self-aligned top via

Extreme ultraviolet (EUV) mask stack processing

Inverse tone pillar printing method using polymer brush grafts

Tunable hardmask for overlayer metrology contrast

Photoactive polymer brush materials and EUV patterning using the same

Organic photoresist adhesion to metal oxide hardmasks

Method to create multilayer microfluidic chips using spin-on carbon as gap fill and spin-on glass tone inversion

Sequential infiltration synthesis extreme ultraviolet single expose patterning

Patterning directly on an amorphous silicon hardmask

Self-priming resist for generic inorganic hardmasks

Spacer-defined process for lithography-etch double patterning for interconnects

Spacer-defined process for lithography-etch double patterning for interconnects

Dynamic adjustment of post exposure bake during lithography utilizing real-time feedback for wafer exposure delay

Multi-channel overlay metrology

Back-end-of-line compatible processing for forming an array of pillars

Embedded etch rate reference layer for enhanced etch time precision

Patterning material film stack with hard mask layer configured to support selective deposition on patterned resist layer

Tunable hardmask for overlayer metrology contrast

Wet strippable OPL using reversible UV crosslinking and de-crosslinking

Integrating gate-cuts and single diffusion break isolation post-RMG using low-temperature protective liners

Method to create multilayer microfluidic chips using spin-on carbon as gap filling materials

Patterning directly on an amorphous silicon hardmask

Simplified block patterning with wet strippable hardmask for high-energy implantation

Post-lithography defect inspection using an e-beam inspection tool

Care area generation by detection optimized methodology

Fabricating electrically nonconductive blocks using a polymer brush and a sequential infiltration synthesis process

Co-optimization of lithographic and etching processes with complementary post exposure bake by laser annealing

AUSSCHNITT CHRISTOPHER P

Self-calibrated alignment and overlay target and measurement

LAM RES CORP

Multi-layer hardmask for defect reduction in EUV patterning