Inventor
SESHADRI INDIRA
US64 patents
Patents
50 patentsUS10304744B1May 28, 2019
Inverse tone direct print EUV lithography enabled by selective material deposition
IBM23 citations94
US10361129B1Jul 23, 2019
Self-aligned double patterning formed fincut
IBM14 citations86
US10176997B1Jan 8, 2019
Direct gate patterning for vertical transport field effect transistor
IBM12 citations84
US10276452B1Apr 30, 2019
Low undercut N-P work function metal patterning in nanosheet replacement metal gate process
IBM13 citations83
US11810828B2Nov 7, 2023
Transistor boundary protection using reversible crosslinking reflow
IBM2 citations73
US11621326B2Apr 4, 2023
Vertical field effect transistor with crosslink fin arrangement
IBM2 citations73
US11251182B2Feb 15, 2022
Staggered stacked vertical crystalline semiconducting channels
IBM2 citations73
US11245027B2Feb 8, 2022
Bottom source/drain etch with fin-cut-last-VTFET
IBM1 citations73
US10741454B2Aug 11, 2020
Boundary protection for CMOS multi-threshold voltage devices
IBM2 citations73
US10678135B2Jun 9, 2020
Surface treatment of titanium containing hardmasks
IBM2 citations73
US10388510B2Aug 20, 2019
Wet strippable OPL using reversible UV crosslinking and de-crosslinking
IBM3 citations73
US10903124B2Jan 26, 2021
Transistor structure with n/p boundary buffer
IBM2 citations72
US10734523B2Aug 4, 2020
Nanosheet substrate to source/drain isolation
IBM6 citations72
US10629495B2Apr 21, 2020
Low undercut N-P work function metal patterning in nanosheet replacement metal gate process
IBM2 citations72
US10395925B2Aug 27, 2019
Patterning material film stack comprising hard mask layer having high metal content interface to resist layer
IBM4 citations71
US12457762B2Oct 28, 2025
Cross bar vertical FETs
IBM0 citations63
US12310100B2May 20, 2025
Dielectric reflow for boundary control
IBM0 citations63
US12107132B2Oct 1, 2024
Source/drain contact positioning under power rail
IBM0 citations63
US12002856B2Jun 4, 2024
Vertical field effect transistor with crosslink fin arrangement
IBM0 citations63
US11916143B2Feb 27, 2024
Vertical transport field-effect transistor with gate patterning
IBM0 citations63
US11855191B2Dec 26, 2023
Vertical FET with contact to gate above active fin
IBM0 citations63
US11646358B2May 9, 2023
Sacrificial fin for contact self-alignment
IBM0 citations63
US11515431B2Nov 29, 2022
Enabling residue free gap fill between nanosheets
IBM0 citations63
US11316029B2Apr 26, 2022
Sacrificial fin for contact self-alignment
IBM0 citations63
US10985025B2Apr 20, 2021
Fin cut profile using fin base liner
IBM0 citations63
US10658521B2May 19, 2020
Enabling residue free gap fill between nanosheets
IBM1 citations63
US12593668B2Mar 31, 2026
Shallow and deep contacts with stitching
IBM0 citations62
US12426320B2Sep 23, 2025
Vertically stacked fin semiconductor devices
IBM0 citations62
US12021135B2Jun 25, 2024
Bottom source/drain etch with fin-cut-last-VTFET
IBM0 citations62
US11990342B2May 21, 2024
Metal cut patterning and etching to minimize interlayer dielectric layer loss
IBM0 citations62
US11756961B2Sep 12, 2023
Staggered stacked vertical crystalline semiconducting channels
IBM0 citations62
US11695059B2Jul 4, 2023
Bottom source/drain etch with fin-cut-last-VTFET
IBM0 citations62
US11556057B2Jan 17, 2023
Surface treatment of titanium containing hardmasks
IBM0 citations62
US11500293B2Nov 15, 2022
Patterning material film stack with hard mask layer configured to support selective deposition on patterned resist layer
IBM0 citations62
US11133189B2Sep 28, 2021
Metal cut patterning and etching to minimize interlayer dielectric layer loss
IBM0 citations62
US11121024B2Sep 14, 2021
Tunable hardmask for overlayer metrology contrast
IBM0 citations62
US11075266B2Jul 27, 2021
Vertically stacked fin semiconductor devices
IBM0 citations62
US11075081B2Jul 27, 2021
Semiconductor device with multiple threshold voltages
IBM0 citations62
US10665461B2May 26, 2020
Semiconductor device with multiple threshold voltages
IBM1 citations62
US12484296B2Nov 25, 2025
Fork sheet device with wrapped source and drain contact to prevent NFET to PFET contact shortage in a tight space
IBM0 citations61
US11569132B2Jan 31, 2023
Transistor structure with N/P boundary buffer
IBM0 citations61
US11226561B2Jan 18, 2022
Self-priming resist for generic inorganic hardmasks
IBM0 citations60
US12362168B2Jul 15, 2025
Solvent annealing of an organic planarization layer
IBM0 citations55
US12374615B2Jul 29, 2025
Electronic devices with a low dielectric constant
IBM0 citations52
US11742426B2Aug 29, 2023
Forming crossbar and non-crossbar transistors on the same substrate
IBM0 citations52
US11710768B2Jul 25, 2023
Hybrid diffusion break with EUV gate patterning
IBM0 citations52
US10818751B2Oct 27, 2020
Nanosheet transistor barrier for electrically isolating the substrate from the source or drain regions
IBM0 citations52
US10741452B2Aug 11, 2020
Controlling fin hardmask cut profile using a sacrificial epitaxial structure
IBM0 citations52
US10734234B2Aug 4, 2020
Metal cut patterning and etching to minimize interlayer dielectric layer loss
IBM0 citations52
US10699912B2Jun 30, 2020
Damage free hardmask strip
IBM0 citations52
Showing the top 50 of 64 patents by PatentIndex Score.