Inventor

KANNAN HARI

US94 patents

⚠️ This page may combine multiple inventors who share the name “KANNAN HARI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KANNAN HARI

PURE STORAGE INC

Optimizing storage device access based on latency

Error recovery in a storage cluster

Page writes for triple level cell flash memory

Die-level monitoring in a storage cluster

Data rebuild on feedback from a queue in a non-volatile solid-state storage

Die-level monitoring in a storage cluster

Intelligent refresh of 3D NAND

Storage system with selectable write paths

Optimal scheduling of flash operations

Adjustable error correction based on memory health in a storage unit

Method for processing blocks of flash memory

Mapping around defective flash memory of a storage array

Transactional commits with hardware assists in remote memory

Masking defective bits in a storage array

Calibration of flash channels in SSD

Hardware support to track and transition flash LUNs into SLC mode

Method and apparatus for artificial intelligence acceleration

Adjusting a variable parameter to increase reliability of stored data

Data rebuild based on solid state memory characteristics

Efficient partitioning for storage system resiliency groups

Write path selection

Selectable write paths with different formatted data

Optimized data resiliency in a modular storage system

Recovering error corrected data

Dynamic block allocation to optimize storage system performance

Resiliency scheme to enhance storage performance

Multi-level cell page writes

Cycled background reads

Die-level monitoring in a storage cluster

Recovering error corrected data

Proactive data rebuild based on queue feedback

Hardware support for non-disruptive upgrades

Die-level monitoring in a storage cluster

Error recovery in a storage cluster

Failure mapping in a storage array

Data rebuild on feedback from a queue in a non-volatile solid-state storage

Failure mapping in a storage array

Storage system with selectable write modes

Online failure span determination

Search acceleration for artificial intelligence

Writing parity data to a targeted wordline

Dynamic buffer for storage system

Page write requirements for a distributed storage system

Latency reduction of flash-based devices using programming interrupts

Error correction incident tracking

Wear levelling for differing memory types

Maintaining coherency in a distributed system

Intelligent operation scheduling based on latency of operations

MICROSOFT CORP

Optimizing systems-on-a-chip using the dynamic critical path

APPLE INC

Load ordering in a weakly-ordered processor