Inventor

LEE CHOONGHYUN

US403 patents

Patents

50 patents

US10700064B1Jun 30, 2020

Multi-threshold voltage gate-all-around field-effect transistor devices with common gates

IBM89 citations98

US10490559B1Nov 26, 2019

Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensions

IBM71 citations98

US10236217B1Mar 19, 2019

Reduction of multi-threshold voltage patterning damage in nanosheet device structure

IBM30 citations94

US10553696B2Feb 4, 2020

Full air-gap spacers for gate-all-around nanosheet field effect transistors

IBM21 citations94

US10535733B2Jan 14, 2020

Method of forming a nanosheet transistor

IBM32 citations94

US10522649B2Dec 31, 2019

Inverse T-shaped contact structures having air gap spacers

IBM23 citations94

US10381438B2Aug 13, 2019

Vertically stacked NFETS and PFETS with gate-all-around structure

IBM25 citations94

US10319846B1Jun 11, 2019

Multiple work function nanosheet field-effect transistors with differential interfacial layer thickness

IBM28 citations94

US10297668B1May 21, 2019

Vertical transport fin field effect transistor with asymmetric channel profile

IBM18 citations94

US10283565B1May 7, 2019

Resistive memory with a plurality of resistive random access memory cells each comprising a transistor and a resistive element

IBM20 citations94

US10276687B1Apr 30, 2019

Formation of self-aligned bottom spacer for vertical transistors

IBM15 citations94

US10229986B1Mar 12, 2019

Vertical transport field-effect transistor including dual layer top spacer

IBM35 citations94

US10115800B1Oct 30, 2018

Vertical fin bipolar junction transistor with high germanium content silicon germanium base

IBM17 citations94

US10002791B1Jun 19, 2018

Multi-layer work function metal gates with similar gate thickness to achieve multi-Vt for vFETS

IBM20 citations94

US9960272B1May 1, 2018

Bottom contact resistance reduction on VFET

IBM27 citations94

US9773875B1Sep 26, 2017

Fabrication of silicon-germanium fin structure having silicon-rich outer surface

IBM21 citations94

US9595449B1Mar 14, 2017

Silicon-germanium semiconductor devices and method of making

IBM22 citations94

US9741822B1Aug 22, 2017

Simplified gate stack process to improve dual channel CMOS performance

IBM14 citations91

US11362193B2Jun 14, 2022

Inverse T-shaped contact structures having air gap spacers

IBM7 citations86

US11152510B2Oct 19, 2021

Long channel optimization for gate-all-around transistors

IBM10 citations86

US10916638B2Feb 9, 2021

Vertical fin field effect transistor devices with reduced top source/drain variability and lower resistance

IBM10 citations86

US10832962B1Nov 10, 2020

Formation of an air gap spacer using sacrificial spacer layer

IBM17 citations86

US10804165B2Oct 13, 2020

Source and drain isolation for CMOS nanosheet with one block mask

IBM12 citations86

US10734447B2Aug 4, 2020

Field-effect transistor unit cells for neural networks with differential weights

IBM12 citations86

US10553678B2Feb 4, 2020

Vertically stacked dual channel nanosheet devices

IBM12 citations86

US10553679B2Feb 4, 2020

Formation of self-limited inner spacer for gate-all-around nanosheet FET

IBM14 citations86

US10497796B1Dec 3, 2019

Vertical transistor with reduced gate length variation

IBM16 citations86

US10332809B1Jun 25, 2019

Method and structure to introduce strain in stack nanosheet field effect transistor

IBM15 citations86

US10325820B1Jun 18, 2019

Source and drain isolation for CMOS nanosheet with one block mask

IBM14 citations86

US10573723B1Feb 25, 2020

Vertical transport FETs with asymmetric channel profiles using dipole layers

IBM12 citations85

US10319833B1Jun 11, 2019

Vertical transport field-effect transistor including air-gap top spacer

IBM15 citations85

US11133309B2Sep 28, 2021

Multi-threshold voltage gate-all-around transistors

IBM6 citations84

US10957778B2Mar 23, 2021

Formation of air gap spacers for reducing parasitic capacitance

IBM4 citations84

US10886368B2Jan 5, 2021

I/O device scheme for gate-all-around transistors

IBM7 citations84

US10886369B2Jan 5, 2021

Formation of self-limited inner spacer for gate-all-around nanosheet FET

IBM8 citations84

US10879352B2Dec 29, 2020

Vertically stacked nFETs and pFETs with gate-all-around structure

IBM9 citations84

US10756216B2Aug 25, 2020

Nanosheet mosfet with isolated source/drain epitaxy and close junction proximity

IBM10 citations84

US10756175B2Aug 25, 2020

Inner spacer formation and contact resistance reduction in nanosheet transistors

IBM10 citations84

US10748994B2Aug 18, 2020

Vertically stacked nFET and pFET with dual work function

IBM7 citations84

US10707304B2Jul 7, 2020

Vertically stacked nFET and pFET with dual work function

IBM5 citations84

US10692866B2Jun 23, 2020

Co-integrated channel and gate formation scheme for nanosheet transistors having separately tuned threshold voltages

IBM7 citations84

US10692873B2Jun 23, 2020

Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensions

IBM6 citations84

US10680083B2Jun 9, 2020

Oxide isolated fin-type field-effect transistors

IBM6 citations84

US10672872B1Jun 2, 2020

Self-aligned base contacts for vertical fin-type bipolar junction transistors

IBM9 citations84

US10658462B2May 19, 2020

Vertically stacked dual channel nanosheet devices

IBM6 citations84

Showing the top 50 of 403 patents by PatentIndex Score.

LEE CHOONGHYUN

Patents

Multi-threshold voltage gate-all-around field-effect transistor devices with common gates

Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensions

Stacked field-effect transistors (FETs) with shared and non-shared gates

Nanosheet with selective dipole diffusion into high-k

I/O device for gate-all-around transistors

Nanosheet electrostatic discharge structure

Multiple dielectrics for gate-all-around transistors

Reduction of multi-threshold voltage patterning damage in nanosheet device structure

Full air-gap spacers for gate-all-around nanosheet field effect transistors

Method of forming a nanosheet transistor

Inverse T-shaped contact structures having air gap spacers

Vertically stacked NFETS and PFETS with gate-all-around structure

Multiple work function nanosheet field-effect transistors with differential interfacial layer thickness

Vertical transport fin field effect transistor with asymmetric channel profile

Resistive memory with a plurality of resistive random access memory cells each comprising a transistor and a resistive element

Formation of self-aligned bottom spacer for vertical transistors

Vertical transport field-effect transistor including dual layer top spacer

Vertical fin bipolar junction transistor with high germanium content silicon germanium base

Multi-layer work function metal gates with similar gate thickness to achieve multi-Vt for vFETS

Bottom contact resistance reduction on VFET

Fabrication of silicon-germanium fin structure having silicon-rich outer surface

Silicon-germanium semiconductor devices and method of making

Simplified gate stack process to improve dual channel CMOS performance

Inverse T-shaped contact structures having air gap spacers

Long channel optimization for gate-all-around transistors

Vertical fin field effect transistor devices with reduced top source/drain variability and lower resistance

Formation of an air gap spacer using sacrificial spacer layer

Source and drain isolation for CMOS nanosheet with one block mask

Field-effect transistor unit cells for neural networks with differential weights

Vertically stacked dual channel nanosheet devices

Formation of self-limited inner spacer for gate-all-around nanosheet FET

Vertical transistor with reduced gate length variation

Method and structure to introduce strain in stack nanosheet field effect transistor

Source and drain isolation for CMOS nanosheet with one block mask

Vertical transport FETs with asymmetric channel profiles using dipole layers

Vertical transport field-effect transistor including air-gap top spacer

Multi-threshold voltage gate-all-around transistors

Formation of air gap spacers for reducing parasitic capacitance

I/O device scheme for gate-all-around transistors

Formation of self-limited inner spacer for gate-all-around nanosheet FET

Vertically stacked nFETs and pFETs with gate-all-around structure

Nanosheet mosfet with isolated source/drain epitaxy and close junction proximity

Inner spacer formation and contact resistance reduction in nanosheet transistors

Vertically stacked nFET and pFET with dual work function

Vertically stacked nFET and pFET with dual work function

Co-integrated channel and gate formation scheme for nanosheet transistors having separately tuned threshold voltages

Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensions

Oxide isolated fin-type field-effect transistors

Self-aligned base contacts for vertical fin-type bipolar junction transistors

Vertically stacked dual channel nanosheet devices