Inventor

OK INJO

US154 patents

⚠️ This page may combine multiple inventors who share the name “OK INJO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OK INJO

IBM

Confined phase change memory with double air gap

Vertical transport fin field effect transistor with asymmetric channel profile

Vertical fin bipolar junction transistor with high germanium content silicon germanium base

Co-integration of different fin pitches for logic and analog devices

Method of forming contact useful in replacement metal gate processing and related semiconductor structure

CMOS NFET and PFET comparable spacer width

Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices

Low resistance replacement metal gate structure

Source and drain isolation for CMOS nanosheet with one block mask

Source and drain isolation for CMOS nanosheet with one block mask

Phase change memory with a patterning scheme for tantalum nitride and silicon nitride layers

Self-aligned base contacts for vertical fin-type bipolar junction transistors

Patterning method for nanosheet transistors

Resistive memory device with electrical gate control

Differential weight reading of an analog memory element in crosspoint array utilizing current subtraction transistors

Vertical vacuum channel transistor with minimized air gap between tip and gate

Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack

Method and structure of improving contact resistance for passive and long channel devices

Nanosheet isolation for bulk CMOS non-planar devices

Stable multiple threshold voltage devices on replacement metal gate CMOS devices

Integrated circuit (IC) with offset gate sidewall contacts and method of manufacture

Self-aligned local interconnect technology

Stable contact on one-sided gate tie-down structure

Minimize middle-of-line contact line shorts

Forming dual contact silicide using metal multi-layer and ion beam mixing

Self heating reduction for analog radio frequency (RF) device

Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices

Semiconductor device having reduced contact resistance

FinFET device formed by a replacement metal-gate method including a gate cut-last step

Phase change memory programming current leakage reduction

Phase change memory cell with a wrap around and ring type of electrode contact and a projection liner

Alignment through topography on intermediate component for memory device patterning

Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between adjacent gates

ILD gap fill for memory device stack array

Complementary metal-oxide-semiconductor (CMOS) nanosheet devices with epitaxial source/drains and replacement metal gate structures

3D phase change memory

Airgap isolation for backend embedded memory stack pillar arrays

Structure and method to form phase change memory cell with self- align top electrode contact

Removal of work function metal wing to improve device yield in vertical FETs

Film stress control for memory device stack

Vertical fin-type bipolar junction transistor with self-aligned base contact

Boosted vertical field-effect transistor

Vertical fin bipolar junction transistor with high germanium content silicon germanium base

Techniques for enhancing vertical gate-all-around FET performance

Method and structure of improving contact resistance for passive and long channel devices

Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack

Self-aligned local interconnect technology

Vertical CMOS devices with common gate stacks

Method and structure of improving contact resistance for passive and long channel devices

HOBBS CHRISTOPHER C

Method for dual-channel nanowire FET device