Inventor

SEO SOON-CHEON

US179 patents

⚠️ This page may combine multiple inventors who share the name “SEO SOON-CHEON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SEO SOON-CHEON

IBM

Process to increase reliability CuBEOL structures

Chip to wiring interface with single metal alloy layer applied to surface of copper interconnect

Vertical transport fin field effect transistor with asymmetric channel profile

Vertical fin bipolar junction transistor with high germanium content silicon germanium base

Co-integration of different fin pitches for logic and analog devices

CMOS NFET and PFET comparable spacer width

Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices

Source and drain isolation for CMOS nanosheet with one block mask

Source and drain isolation for CMOS nanosheet with one block mask

Self-aligned base contacts for vertical fin-type bipolar junction transistors

Resistive memory device with electrical gate control

Differential weight reading of an analog memory element in crosspoint array utilizing current subtraction transistors

Vertical vacuum channel transistor with minimized air gap between tip and gate

Extended contact area using undercut silicide extensions

Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack

Nanowire FET including nanowire channel spacers

Method and structure of improving contact resistance for passive and long channel devices

Nanosheet isolation for bulk CMOS non-planar devices

Integrated circuit (IC) with offset gate sidewall contacts and method of manufacture

Stable contact on one-sided gate tie-down structure

Minimize middle-of-line contact line shorts

Forming dual contact silicide using metal multi-layer and ion beam mixing

Salicide formation on replacement metal gate finFet devices

Semiconductor devices with sidewall spacers of equal thickness

Spacer for dual epi CMOS devices

Self heating reduction for analog radio frequency (RF) device

Semiconductor devices with sidewall spacers of equal thickness

Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices

Semiconductor device with trench epitaxy and contact

FinFET with dielectric isolated channel

PE-ALD of TaN diffusion barrier region on low-k materials

Chromium adhesion layer for copper vias in low-k technology

Removal of trilayer resist without damage to underlying structure

Spacer formation on semiconductor device

Phase change memory programming current leakage reduction

Non volatile resistive memory logic device

Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between adjacent gates

ILD gap fill for memory device stack array

Airgap isolation for backend embedded memory stack pillar arrays

Complementary metal-oxide-semiconductor (CMOS) nanosheet devices with epitaxial source/drains and replacement metal gate structures

Removal of work function metal wing to improve device yield in vertical FETs

Film stress control for memory device stack

INFINEON TECHNOLOGIES AG

Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer

Bilayer HDP CVD/PE CVD cap in advance BEOL interconnect structures and method thereof

Bilayer HDP CVD/PE CVD cap in advanced BEOL interconnect structures and method thereof

GLOBALFOUNDRIES INC

FinFET spacer formation on gate sidewalls, between the channel and source/drain regions

Methods of patterning features having differing widths

STANDAERT THEODORUS EDUARDUS

FinFET with improved gate planarity

SEO SOON-CHEON

MOSFET gate and source/drain contact metallization

KELLY JAMES J

Superfilled metal contact vias for semiconductor devices