Inventor

IYER VENKATRAMAN

US102 patents

⚠️ This page may combine multiple inventors who share the name “IYER VENKATRAMAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IYER VENKATRAMAN

INTEL CORP

Multichip package link error detection

High performance interconnect

High performance interconnect physical layer

High performance interconnect physical layer

High performance interconnect physical layer

Method and apparatus for high speed signaling

Signal repeater for voltage intolerant components used in a serial data line

High performance interconnect

High performance interconnect physical layer

High performance interconnect physical layer

Link-physical layer interface adapter

High performance interconnect physical layer

Redriver link testing

High performance interconnect physical layer

Fast deskew when exiting low-power partial-width high speed link state

High performance interconnect

Low latency retimer

High performance interconnect

Multichip package link

Method, apparatus, system for centering in a high performance interconnect

High performance interconnect physical layer

Multichip package link error detection

Multichip package link error detection

High performance interconnect physical layer

Multichip package link error detection

Bimodal PHY for low latency in high speed interconnects

High speed interconnect with channel extension

High performance interconnect physical layer

Bimodal phy for low latency in high speed interconnects

High performance interconnect physical layer

Bimodal PHY for low latency in high speed interconnects

High performance repeater

High performance interconnect physical layer

Low power entry in a shared memory link

ADVANCED MICRO DEVICES INC

RAM buffer controller for providing simulated first-in-first-out (FIFO) buffers in a random access memory

Improved pointer FIFO controller for converting a standard RAM into a simulated dual FIFO by controlling the RAM&#39;s address inputs

CRC calculation machine with variable bit boundary

CRC calculation machine for separate calculation of checkbits for the header packet and data packet

Processor to peripheral interface for asynchronous or synchronous applications

Linear feedback shift register for circuit design technology validation

CRC calculation apparatus having reduced output bus size

KLA TENCOR CORP

Anti-reflection layer for back-illuminated sensor

Anti-reflection layer for back-illuminated sensor

Scanning electron microscope and methods of inspecting and reviewing samples

Scanning electron microscope and methods of inspecting and reviewing samples

Interposer based imaging sensor for high-speed image acquisition and inspection systems

IYER VENKATRAMAN

Embedded control channel for high speed serial interconnect

Enhanced interconnect link width modulation for power savings

BROWN DAVID L

Integrated multi-channel analog front end and digitizer for high speed imaging applications

CHERUKURI NAVEEN

Link power savings with state retention

Improved pointer FIFO controller for converting a standard RAM into a simulated dual FIFO by controlling the RAM's address inputs